Abstract: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.

Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Abstract: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.

Abstract: A polysilicon resistor fuse has an elongated bow-tie body that is wider at the opposite ends relative to a narrow central portion. The opposite ends of the body of the fuse have high concentrations of N-type dopants to make them low resistance contacts. The upper portion of the central body has a graded concentration of N-type dopants that decreases in a direction from the top surface toward the middle of the body between the opposite surfaces. The lower central portion of the body is lightly doped with P-type dopants. The central N-type region is a resistive region.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: A size variable semiconductor chip includes a semiconductor chip area formed with a circuit layer and at least one cutting area extending parallel to at least one side of the semiconductor chip area. A plurality of scribe line parts and a plurality of active parts alternately formed with each other in the cutting area.

Abstract: A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.

Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

Abstract: An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented in a (111) plane; and a second orientation film which contains copper as a main component and is oriented in a (511) plane. The second orientation film is provided inside the first orientation film over a width direction of the first orientation film, which is perpendicular to a direction from the first terminal toward the second terminal, so as to partition the first orientation film. Accordingly, it becomes possible to securely cut the electrical fuse whose constituent material is copper, and moreover, to maintain a satisfactory cut state of the electrical fuse after the cutting.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.

Abstract: A semiconductor device having an electrical fuse which is cut in a reliable manner and a method for manufacturing it. The electrical fuse is a multilayer structure which includes a polysilicon film and a metal silicide film such as a tungsten silicide film. By applying an electric current with a density of 40 mA/?m3 or more to the electrical fuse with a prescribed length, the fuse is cut by electromigration and a pinch effect in a reliable manner.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first line, a second line spaced apart from the first line, a contact formed over the first line and the second line, a fuse coupled to the contact, and a dummy pattern configured to couple the fuse to the contact.

Abstract: In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.

Abstract: A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.

Abstract: A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have been formed, a conductive target, such as an aluminum target, is formed on the copper target structure at the same time that conductive connection portions, such as aluminum pads, are formed on the copper traces. A trench is then etched around the copper target structure and conductive target to form a fuse target.

Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.

Abstract: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

Abstract: A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment.

Abstract: A non-volatile latch circuit is provided. The non-volatile latch circuit includes a nanotube switching element capable of switching between resistance states and non-volatilely retaining the resistance state. The non-volatile latch circuit includes a volatile latch circuit is capable of receiving and volatilely storing a logic state. When the nanotube switching element is a resistance state, the volatile latch circuit retains a corresponding logic state and outputs that corresponding logic state at an output terminal. A non-volatile register file configuration circuit for use with a plurality of non-volatile register files is also provided. The non-volatile register file configuration circuit includes a selection circuitry and a plurality of nanotube fuse elements, each in electrical communication with one of a plurality of non-volatile register files.

Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.

Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

Abstract: A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

Abstract: A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.

Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern. The conductive polymer layer includes a nano-sized metal powder and a polymer.

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure of a semiconductor substrate, an upper conductive film of the multilayer interconnection spaced apart upward from the lower conductive film to define a predetermined vertical space therebetween, and a contact electrode, which vertically connects the upper and lower conductive films to each other and forms a fuse body. The lower conductive film includes a form not coinciding with that of the upper conductive film. With such a configuration, the device can achieve a stable minimization in the length of the fuse and the distance between adjacent fuses in consideration of a laser beam irradiation region for the high integration of the semiconductor memory device. In this way, the device performs the repair process of cutting the contact electrode and/or upper conductive film using a laser beam.

Abstract: A semiconductor device that includes a metal fuse which may be used for redundancy or trimming, allowing for adjustment in the characteristics of a circuit. The fuse includes a disconnecting metal, a plurality of metal-vias that are connected under respective ends of the disconnecting metal, and a plurality of interconnections that connect to the disconnecting metal through respective metal-vias. The disconnecting metal is disconnected by a laser exposure and the metal-vias are located inside of the spot diameter of the laser used for the laser exposure, and are spaced apart from a side surface of the disconnecting metal. The disconnecting metal is formed of a material having a melting point and a boiling point that is lower than the melting point and boiling point of the metal-vias.

Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Abstract: A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.

Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.

Abstract: A fuse target is fabricated in a copper process by forming a number of copper targets at the same time that the copper traces are formed. After the copper targets and the copper traces have been formed, metal targets, such as aluminum targets, are formed on the copper targets at the same time that metal bonding pads, such as aluminum bonding pads, are formed on the copper traces.