Abstract: A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by vias provided respectively above and below the power supply ring. Consequently, even if the width of the pad is narrowed, the number of vias disposed to connect the pad for the power supply and the power supply ring can be at least doubled compared to the conventional one to increase the amount of a current which can be provided to the power supply ring, which makes it possible to provide the sufficient current from outside to the power supply ring even in the semiconductor device with the narrow-width pad.

Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.

Abstract: An integrated circuit is provided with a first power line, a plurality of additional power lines intersecting with the first power line, a plurality of power switch transistors each having a drain connected with the first power line and a source connected with one of the additional power lines, a well provided to extend along the first power line; and a plurality of primitive cells each including a first transistor prepared within the well, the first transistor having a source connected with the first power line. The plurality of additional power lines includes first and second additional power lines The plurality of primitive cells are provided between the first and second additional power lines along the first power line. A bias voltage is fed to the well through both of first and second well contacts, the first well contact providing a connection between the first additional power line and the well, and the second well contact providing a connection between the second additional power line and the well.

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: An example of a high-frequency semiconductor device includes two unit semiconductor devices. Each of the two unit semiconductor devices has a ground substrate, a high-frequency semiconductor element, an input-side matching circuit, an output-side matching circuit, a side wall member, an input terminal, and an output terminal. The ground substrate has heat-radiating property. The high-frequency semiconductor element is provided on the ground substrate. The input-side matching circuit is connected to the high-frequency semiconductor element. The output-side matching circuit is connected to the high-frequency semiconductor element. The side wall member surrounds at least the high-frequency semiconductor element. The input terminal is connected to the input-side matching circuit. The output terminal is connected to the output-side matching circuit. The two unit semiconductor devices are coupled to each other at upper edges of the side wall members.

Abstract: In a printed circuit board, a semiconductor including plural power supply terminals and a semiconductor chip is mounted onto a mounting surface of a printed wiring board, and a bypass capacitor for reducting a power ground noise is provided. Another bypass capacitor, which is connected to the bypass capacitor only within an IC chip is provided to inhibit the power ground noise from causing not only a variation in timing of the IC chip and a malfunction thereof but also a malfunction of another IC chip and the generation of an EMI noise in a case where the power ground noise propagates to a power supply side.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

Abstract: Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit is subdivided into core functionality and peripheral functionality, and the carrier substrate is subdivided into a corresponding core area and peripheral area. The ground connections of both core and periphery are mutually coupled through an interconnect in the carrier substrate. This interconnect is particularly a ground plane, and allows the provision of a transmission line character to the interconnects for signal transmission of the periphery.

Abstract: A switch device includes a semiconductor chip, and at least two switches formed on the semiconductor chip. Ground parts of the at least two switches are arranged between said at least two switches.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of second metal lines are formed on the first metal layer and connected with a ground voltage. The second metal lines are arranged neighboring to the first metal lines. The second metal lines are connected with a second metal layer disposed below the first metal lines on the metal layer, and the first metal lines are connected with the second metal layer disposed below the second metal lines on the first metal layer. An insulating layer is disposed between the first metal layer and the second metal layer, thereby forming a decoupling capacitance between the first metal lines and the second metal lines.

Abstract: A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals 151 and output terminals 152 for connecting the cell to another cell are formed includes a power supply line passing region 153 through which a power supply line for supplying a power supply voltage and a ground voltage from an external power supply to the transistors in the cell can be provided.

Abstract: A semiconductor device (1) comprises a semiconductor substrate (2) on which an integrated circuit (3, 4) is formed, a first ground terminal (7) and a second ground terminal (8) for electrically connecting the integrated circuit (3, 4) to an external ground electrode, and an electrostatic breakdown protection element (5) for electrically connecting the first ground terminal (7) with the second ground terminal (8). The first ground terminal (7) is electrically connected with the semiconductor substrate (2), while the second ground terminal (8) is not electrically connected with the semiconductor substrate (2). A semiconductor device comprises a semiconductor substrate on which an integrated circuit is formed, a first ground terminal and a second ground terminal for electrically connecting the integrated circuit to an external ground electrode, and an electrostatic breakdown protection element for electrically connecting the first ground terminal with the second ground terminal.

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.

Abstract: A composite electronic component having a multi-layer wiring board, a first power terminal electrode, a second power terminal electrode, an external connection power supply terminal, a surface-mounted component, an insulator, and a power supply pattern. The first and the second power terminal electrodes are disposed on a first face of the multi-layer wiring board. The external connection power supply terminal is disposed on a second face opposite to the first face of the multi-layer wiring board and connected with the first power terminal electrode. The surface-mounted component is mounted on the first face of the multi-layer wiring board and connected with the first and the second power terminal electrodes at a first face thereof. The insulator covers at least a second face opposite to the first face of the surface-mounted component, the first power terminal electrode, and the second power terminal electrode with a first face thereof.

Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.

Abstract: A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.

Abstract: A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n?2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

Abstract: Disclosed are methods for making microwave circuits using thickfilm components. In an embodiment, the method includes depositing a dielectric over a ground plane, and then forming a conductor on the dielectric. The conductor is formed by depositing a conductive thickfilm on the dielectric and then “subsintering” the conductive thickfilm. In one embodiment, before the subsintering, the conductive thickfilm is patterned to define at least one conductor. In another embodiment, after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired at a full sintering temperature.

Abstract: The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

Abstract: Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. In an embodiment, a transmission line is disposed on a first layer of insulating material, where the first layer of insulating has a thickness equal to or less than 1.0 micrometer. The transmission line may be structured with a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is disposed on the transmission line.

Abstract: In a method for making a microwave circuit, a first dielectric is deposited over a ground plane, and then a conductor is formed on the first dielectric. A second dielectric is then deposited over the conductor and first dielectric, thereby encapsulating the conductor between the first and second dielectrics. In one embodiment, a ground shield layer is formed over the first and second dielectrics by 1) precoating the first and second dielectrics with a metallo-organic layer, and then 2) depositing a thickfilm ground shield layer over the precoat layer. Alternately, a ground shield layer is formed over the first and second dielectrics by 1) placing a polymer screen over the first and second dielectrics, and applying pressure to the polymer screen until it at least partially conforms to a contour of the dielectrics, and then 2) printing a thickfilm ground shield layer through the polymer screen.

Abstract: Crosstalk is suppressed low even when one surface of a multi-layer board seats a semiconductor integrated circuit of the BGA type and peripheral circuit components. Of a plurality of BGA bumps arranged on the back surface of a semiconductor integrated circuit chip, those BGA bumps (such as a high-frequency signal pin) to which peripheral circuit components need be mounted right close are arranged outer-most, and peripheral circuit components are then mounted right close to these BGA bumps. The BGA bumps one tier inner from the outer-most BGA bumps, which are to be used as grounding terminals, are connected with a wide inner-layer grounding wire pattern. Those BGA bumps (such as a logic control signal pin) to which peripheral circuit components need not be mounted right close are disposed further inward and connected with an inner-layer wire pattern which is located even deeper down from a front layer.

Abstract: A semiconductor device that achieves high speed and low power consumption that can be used in a real-time system by preventing held data from disappearing at the time of power shutdown and sharply rising power while also preventing a through-current at the time of power resumption. During normal operation, the switch is on, and the clock generating circuit and the data holding circuit are operated with the first power supply voltage. When data holding is required at the time of power shutdown, the switch and the first power supply voltage supplied to the logic circuit are turned off, and the clock generating circuit and the data holding circuit are operated with the second power supply voltage.