Abstract: A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: Disclosed is an avalanche photodiode using a silicon nanowire, including a first silicon nanowire formed of silicon (Si), a first conductive region formed by doping one surface of the first silicon nanowire with a first dopant, and a second conductive region formed by doping one surface of the first silicon nanowire with a second dopant having a conductive type different from that of the first dopant so as to be arranged continuously in a longitudinal direction from the first conductive region, wherein, when the magnitude of a reverse voltage applied to both ends of the first silicon nanowire is equal to or greater than a preset breakdown voltage, avalanche multiplication of inner current occurs due to the incidence of light from the outside.

Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

Abstract: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided.

Abstract: According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.

Abstract: A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.

Abstract: A dynamic and noninvasive method of monitoring the adhesion and proliferation of biological cells through multimode operation (acoustic and optical) using a ZnO nanostructure-modified quartz crystal microbalance (ZnOnano-QCM) biosensor is disclosed.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer.

Abstract: A sensing device includes a nanowire configured to deform upon exposure to a force, and a transducer for converting the deformation into a measurement. The nanowire has two opposed ends; and the transducer is operatively connected to one of the two opposed ends of the nanowire. The other of the two opposed ends of the nanowire is freestanding.

Abstract: An electrical connection structure having elongated carbon structures electrically connected to an electroconductive body is obtained by successively layering an electroconductive catalyst support layer, a fine catalyst particle layer for producing the elongated carbon structures and the elongated carbon structures on the electroconductive body. A low-resistance electrical connection structure is provided.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.

Abstract: The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nanotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nanotubes are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.

Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.

Abstract: An electronic component comprises a plurality of layers at least two of which comprise predominantly organic functional materials with improved through-plating through certain of the layers. The through-plating is formed in one embodiment by a disruption element on a first lower layer which results in a void in the subsequently applied layers, which void is filled with a material which may be conductive to form the through plating. In a second embodiment, the through plating is formed on the first lower layer prior to the subsequent application of the other layers, in the form of a free-standing truncated frusto-conical raised portion, and forms a disruption or non-welting element for the subsequently applied other layers, formed on the first lower layer and which are engaged with and surround the through plating after their application.

Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.

Abstract: The present invention provides the multifunctional biological and biochemical sensor technology based on the integration of ZnO nanotips with bulk acoustic wave (BAW) devices, particularly, quartz crystal microbalance (QCM) and thin film bulk acoustic wave resonator (TFBAR). ZnO nanotips provide giant effective surface area and strong bonding sites. Furthermore, the controllable wettability of ZnO nanostructured surface dramatically reduces the liquid consumption and enhances the sensitivity of the biosensor device.

Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

Abstract: Under one aspect, non-volatile transistor device includes a source and drain with a channel in between; a gate structure made of a semiconductive or conductive material disposed over an insulator over the channel; a control gate made of a semiconductive or conductive material; and an electromechanically-deflectable nanotube switching element in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region.

Abstract: A layer to enhance nucleation of a substrate is described, including a method to form the layer, the method including obtaining a substrate comprising a patterned feature comprising a dielectric region and a conductive region, selectively forming a self-aligned monolayer (SAM) on the dielectric region of the substrate to enhance nucleation process of a first precursor, and depositing the first precursor on the substrate, the precursor to adsorb on the SAM.

Abstract: A bond pad structure (300) for an integrated circuit (IC) device uses carbon nanotubes to increase the strength and resilience of wire bonds (360). In an example embodiment there is, a bond pad structure (300) on an IC substrate, the bond pad structure comprises, a first conductive layer (310) having a top surface and a bottom surface, the bottom surface attached to the IC substrate. A dielectric layer (320) is deposited on the top surface of the first conductive layer (310), the dielectric layer having an array of vias (325), the array of vias filled with a carbon nanotube material (325), the carbon nanotube material (325) is electrically coupled to the first conductive layer (310). There is a second conductive layer (330) having a top surface and a bottom surface, the bottom surface of the second conductive layer is electrically coupled to the carbon nanotube material (325).

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: An integrated circuit (IC) includes an interconnect system made of electrically conducting ribtan material. The integrated circuit includes a substrate, a set of circuit elements that are formed on the substrate, an interconnect system that interconnects the circuit elements. At least part of the interconnect system is made of a metallic ribtan material.

Abstract: A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.

Abstract: In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.

Abstract: An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 ?A to approximately 150 ?A.

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract: A microelectronic device and a method for producing the device can overcome the disadvantages of known electronic devices composed of carbon molecules, and can deliver performance superior to the known devices. An insulated-gate field-effect transistor includes a multi-walled carbon nanotube (10) having an outer semiconductive carbon nanotube layer (1) and an inner metallic carbon nanotube layer (2) that is partially covered by the outer semiconductive carbon nanotube layer (1). A metal source electrode (3) and a metal drain electrode (5) are brought into contact with both ends of the semiconductive carbon nanotube layer (1) while a metal gate electrode (4) is brought into contact with the metallic carbon nanotube layer (2). The space between the semiconductive carbon nanotube layer (1) and the metallic carbon nanotube layer (2) is used as a gate insulating layer.

Abstract: An apparatus includes a plurality of wash durable clothing strands; an array of nano electronic elements fabricated in the strands; and an array of memory elements coupled to the nano electronic elements. The nano electronic elements can include solar cells, display elements, or antennas, among others.

Abstract: For semiconductor chips (1) using thin film technology, an active layer sequence (20) is applied to a growth substrate (3), on which a reflective electrically conductive contact material layer (40) is then formed. The active layer sequence is patterned to form active layer stacks (2), and reflective electrically conductive contact material layer (40) is patterned to be located on each active layer stack (2). Then, a flexible, electrically conductive foil (6) is applied to the contact material layers as an auxiliary carrier layer, and the growth substrate is removed.

Abstract: A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated circuitry includes forming a step wall over a semiconductor substrate. Catalytic material is provided proximate the step wall. An elevationally outer surface of the catalytic material is masked with a masking material. The catalytic material and the masking material are patterned to form an exposed end sidewall of the catalytic material proximate the step wall, with remaining of the elevationally outer surface of the catalytic material being masked. A carbon nanotube is grown from the exposed end sidewall of the catalytic material along the step wall generally parallel to the semiconductor substrate. The carbon nanotube is incorporated into a circuit component of an integrated circuit.

Abstract: A semiconductor device and fabricating method thereof are provided. A carbon interconnection line can be formed on an interlayer insulating layer such that the carbon interconnection line is electrically connected to a conductive metal layer disposed in a contact hole of the semiconductor device.

Abstract: A semiconductor device having upright dielectric nanotubes at an inter-layer dielectric level and method of manufacturing such a device is disclosed. The use of a catalyst is proposed in the disclosed manufacturing flow that facilitates growth of upright dielectric nanotubes having ultra low-k values that form all or part of the dielectric material for an ILD. In one embodiment, carbon nanotubes form interlayer conducting vias. In another embodiment dielectric material nanotubes form reinforcing pillars. The integration of catalysts is proposed to accommodate both upright dielectric and upright conducting nanotube fabrication in the same layer.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.

Abstract: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.

Abstract: A plastic package and to a semiconductor component including such a plastic package, as well as to a method for its production is disclosed. In one embodiment, the plastic package includes plastic outer faces, which include lower outer contact faces on a lower side of the plastic package and upper outer contact faces on an upper side, which are connected together via outer conductor tracks. The conductor tracks include conduction paths which are formed on exposed conducting deposits in the plastic package.

Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

Abstract: A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N?1 electrically conductive regions to touch the electrically conductive layer.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: An integrated circuit package includes a die mounted on a substrate, an integrated heat spreader set above the die, and an array of carbon nanotubes mounted between the die and the integrated heat spreader. The integrated heat spreader is fixed on the substrate, and includes an inner face. The array of carbon nanotubes is formed on the inner face of the integrated heat spreader. Top and bottom ends of the carbon nanotubes perpendicularly contact the integrated heat spreader and the die respectively. Each carbon nanotube can be capsulated in a nanometer-scale metal having a high heat conduction coefficient.

Abstract: Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure.