Abstract: A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

Abstract: A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire.

Abstract: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.

Abstract: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.

Abstract: An upper electrode film includes a first conductive oxidation layer made of an oxide expressed by a chemical formula M1Ox2, a second conductive oxidation layer made of an oxide expressed by a chemical formula M2Oy2 and a third conductive oxidation layer. Here, the second conductive oxidation layer is formed to have a degree of oxidation higher than the first conductive oxidation layer and the third conductive oxidation layer, and among the composition parameters x1, x2, y1, y2, z1 and z2, there are the following relations, y2/y1>x2/x1, y2/y1>z2/z1, and z2/z1?x2/x1.

Abstract: A ferroelectric capacitor includes a lower electrode, a ferroelectric film provided over the lower electrode and having a perovskite-type structure and an upper electrode provided over the ferroelectric film. The ferroelectric film includes a first ferroelectric film part having a first crystal system and formed along at least one interface with at least one of the lower electrode and the upper electrode and a second ferroelectric film part having a second crystal system that is different from the first crystal system.

Abstract: A CMOS image sensor and fabricating method thereof by which capacitance of a floating diffusion region (FD) can be increased.

Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract: An electrostatic discharge protection element is disclosed for protecting an internal circuit from electrostatic current. The electrostatic discharge protection element forms an embedded LVTSCR by adding a prescribed impurity region within an N-well region having a P-type diode formed therein. A P-well region having a GGNMOS transistor is also formed in the electrostatic discharge protection element. The embedded LVTSCR improves area efficiency, reduces a resistance, and lowers an operational voltage by reducing the distance between the P-type diode and the LVTSCR to allow high-speed operatation.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

Abstract: A silicon-made low-forward-voltage Schottky barrier diode is serially combined with a high-antivoltage-strength high-electron-mobility transistor made from a nitride semiconductor that is wider in bandgap than silicon. The Schottky barrier diode has its anode connected to the gate, and its cathode to the source, of the HEMT. This HEMT is normally on. The reverse voltage withstanding capability of the complete device depends upon that between the drain and gate of the HEMT.

Abstract: A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the first trench and the second trench. A first capacitor dielectric layer and a second capacitor dielectric layer are formed on the respective surfaces of the first trench and the second trench. A first upper electrode and a second upper electrode are formed to fill the first trench and the second trench. A portion of the isolation structure between the first trench and the second trench is removed to form an opening. A conductive layer is formed to fill the opening and connect electrically with the first upper electrode and the second upper electrode.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: Disclosed herewith is a semiconductor device comprising a trench gate electrode and a zener diode, as well as a method for manufacturing the same. The trench gate electrode is formed in a semiconductor body and includes a first polycrystalline silicon layer doped with impurities of a first conductivity type at a first concentration. An extended gate electrode is elongated over the semiconductor body in contact with the trench gate electrode, and includes a second polycrystalline silicon layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration. The zener diode is formed over the semiconductor body and includes a third polycrystalline silicon layer of a first conductivity type and a fourth polycrystalline silicon layer of a second conductivity type.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.

Abstract: In a semiconductor device and a method of fabrication thereof, a semiconductor device comprises a substrate including transistors and partitioned into a memory region and a logic region. A bit line is electrically connected to at least one of the transistors in the memory region. A logic capacitor is formed on the logic region. The logic capacitor includes a logic lower metal electrode of a same layer as that of the bit line, a logic dielectric film, and a logic upper metal electrode.

Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.

Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.

Abstract: A semiconductor device has a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area. The termination structure comprises a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode. The termination structure (16) is capable of withstanding higher voltages in a compact manner and features thereof are susceptible to fabrication in the same process steps as features of the active area (7).

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: An integrated circuit used in smart power technology, in particular, for use in automobile applications, which includes: high-voltage terminals for connection to a high voltage, a smart circuit device having low-voltage components, and an ESD protective circuit, connected between the high-voltage terminals, which has a MOSFET whose source and drain are connected to the high-voltage terminals, and whose gate is connected to its source via a resistor, the gate resistor being made of polycrystalline silicon. High ESD resistance with relatively low surface area usage and accordingly low costs may be achieved by using the polyresistor as the gate resistor. One protective diode, which blocks above the supply voltage, may be connected in the blocking direction between source and gate and between gate and drain of the MOSFET.

Abstract: There is provided a high-voltage-withstanding semiconductor device a fabrication method thereof capable of suppressing Vt fluctuation induced by plasma damage in a via hole forming step. In the high-voltage-withstanding semiconductor device, a gate electrode of a transistor having a gate insulating film formed on a semiconductor substrate and having a thickness of 350 ? or more and a diode composed of a first conductive well region formed in a surface layer region of the semiconductor substrate and a second conductive diffusion layer formed in the surface layer region of the semiconductor substrate and on the well region are electrically connected by a wire directly connected to contacts formed respectively on the gate electrode and the diode, via the contacts.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.

Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

Abstract: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a capacitor formed above the first silicide film and electrically connected to the first silicide film; and a second silicide film formed in an upper surface of the fourth impurity region and having a larger t

Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.

Abstract: In a capacitor device of the present invention, a capacitor parts that has a pair of terminals on both end sides respectively is embedded in an insulating film in a state that a lower surface of the capacitor parts is not covered with the insulating film, then upper wiring patterns that are connected to upper surfaces of a pair of terminals via holes formed in the insulating film on a pair of terminals are formed on an upper surface side of the insulating film respectively, and then lower wiring patterns that are connected to lower surfaces of a pair of terminals are formed on a lower surface side of the insulating film respectively.

Abstract: A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer formed in a plane shape on a semiconductor substrate, and the shield layer is electrically connected directly to the semiconductor substrate and is fixed to a power supply potential or the ground potential.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract: A semiconductor integrated circuit device includes at least one MOS transistor that is formed in a main region of the circuit device. The main region has one conductivity type. The semiconductor integrated circuit device also includes a guard ring region formed surrounding the MOS transistor and in contact with the main region. The guard ring has the same conductivity type as the main region. The semiconductor integrated circuit device further includes an anode region formed facing the guard ring region and in contact with the main region. The anode region has the opposite conductivity type to the main region. The semiconductor integrated circuit device also includes a cathode region having at least a portion of the guard ring region. The anode region, the main region, and the cathode region form a diode.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A rectifier MESFET includes an N-channel MESFET having its gate connected to its source, and at the same current density having a voltage drop lower than the gate Schottky diode. A Schottky diode may be connected in parallel with the N-channel device to provide over current protection. A Zener may also be connected in parallel to provide reverse voltage protection. A second N-channel device may be connected in parallel. The addition of the second N-channel provides two different operational mode: synchronous rectification where the majority of current flows through the low resistance first N-channel device and asynchronous rectification where the majority of current flows through the somewhat higher resistance first N-channel device.

Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.

Abstract: A semiconductor device include an emitter layer, an emitter electrode containing a metal-semiconductor compound of a metal and a semiconductor, formed on a surface of the emitter layer, and a first reaction suppression layer formed between the emitter layer and the emitter electrode and suppressing permeation of the metal diffused from the emitter electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.