In Combination With Diode, Resistor, Or Capacitor (epo) Patents (Class 257/E27.016)
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Publication number: 20120161248Abstract: A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Patrick M. Shea, Samuel J. Anderson
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Publication number: 20120161224Abstract: A semiconductor device includes a cathode and an anode. The anode includes a first p-type semiconductor anode region and a second p-type semiconductor anode region. The first p-type semiconductor anode region is electrically connected to an anode contact area. The second p-type semiconductor anode region is electrically coupled to the anode contact area via a switch configured to provide an electrical connection or an electrical disconnection between the second p-type anode region and the anode contact area.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Hans-Günter Eckel, Jörg Schumann
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Patent number: 8207564Abstract: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The shared digitline couples with adjacent memory cells, and the plurality of access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in a substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.Type: GrantFiled: July 27, 2010Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventors: H. Montgomery Manning, David H. Wells
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Patent number: 8207565Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.Type: GrantFiled: November 20, 2009Date of Patent: June 26, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Sato
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Publication number: 20120153396Abstract: According to an embodiment, a semiconductor device including a switch circuit includes a first gate electrode provided between a source region and a drain region of an FET and a second gate electrode provided between the first gate electrode and the drain region. The semiconductor device also includes a control terminal electrically connected to an intermediate region between the first gate electrode and the second gate electrode, the control terminal being placed at a ground potential corresponding to ON state of the FET, and the control terminal being placed at a positive potential or a negative potential corresponding to OFF state of the FET.Type: ApplicationFiled: September 8, 2011Publication date: June 21, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masayuki Sugiura, Toshiki Seshita, Yoshimoto Sagae
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Publication number: 20120153370Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.Type: ApplicationFiled: February 28, 2012Publication date: June 21, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi FURUTA, Takayuki Shirai, Shunsaku Naga
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Patent number: 8203175Abstract: A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.Type: GrantFiled: December 29, 2009Date of Patent: June 19, 2012Assignee: Sony CorporationInventor: Hideaki Kuroda
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Patent number: 8203135Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.Type: GrantFiled: February 1, 2010Date of Patent: June 19, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Rie Sim, Jung-Hoon Park, Yoon-Jong Song, Jae-Min Shin, Shin-Hee Han
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Publication number: 20120146105Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: ApplicationFiled: February 10, 2012Publication date: June 14, 2012Applicant: Power Integrations, Inc.Inventors: Sujit Banerjee, Vijay Parthasarathy
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Publication number: 20120146185Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.Type: ApplicationFiled: February 14, 2012Publication date: June 14, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kouichi Nagai
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Publication number: 20120138921Abstract: A conductive film to be a gate electrode, a first insulating film to be a gate insulating film, a semiconductor film in which a channel region is formed, and a second insulating film to be a channel protective film are successively formed. With the use of a resist mask formed by performing light exposure with the use of a photomask which is a multi-tone mask and development, i) in a region without the resist mask, the second insulating film, the semiconductor film, the first insulating film, and the conductive film are successively etched, ii) the resist mask is made to recede by ashing or the like and only the region of the resist mask with small thickness is removed, so that part of the second insulating film is exposed, and iii) the exposed part of the second insulating film is etched, so that a pair of opening portions is formed.Type: ApplicationFiled: November 18, 2011Publication date: June 7, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yuta ENDO, Kosei NODA
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Publication number: 20120138954Abstract: According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.Type: ApplicationFiled: June 20, 2011Publication date: June 7, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazutaka TAKAGI
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Patent number: 8193066Abstract: In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times.Type: GrantFiled: June 3, 2009Date of Patent: June 5, 2012Assignee: Globalfoundries Inc.Inventors: Andreas Kurz, Roman Boschke, Christoph Schwan, John Morgan
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Patent number: 8193565Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.Type: GrantFiled: April 17, 2009Date of Patent: June 5, 2012Assignee: Fairchild Semiconductor CorporationInventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
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Publication number: 20120132969Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.Type: ApplicationFiled: November 23, 2011Publication date: May 31, 2012Applicant: NXP B.V.Inventors: Lukas Frederik Tiemeijer, Vittorio Cuoco, Rob Mathijs Heeres, Jan Anne van Steenwijk, Marnix Bernard Willemsen, Josephus Henricus Bartholomeus van der Zanden
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Publication number: 20120132954Abstract: A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.Type: ApplicationFiled: November 22, 2011Publication date: May 31, 2012Applicant: DENSO CORPORATIONInventors: Kenji KOUNO, Hiromitsu Tanabe, Yukio Tsuzuki
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Publication number: 20120132995Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20120132970Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof.Type: ApplicationFiled: November 29, 2011Publication date: May 31, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Jongchul PARK, Sangsup Jeong, Byung-Jin Kang
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Publication number: 20120132973Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.Type: ApplicationFiled: January 23, 2012Publication date: May 31, 2012Applicant: TRANSPHORM INC.Inventor: Yifeng Wu
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Publication number: 20120126335Abstract: A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. CHUDZIK, Ricardo A. DONATON, William K. HENSON, Yue LIANG
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Patent number: 8178915Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.Type: GrantFiled: March 23, 2011Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
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Patent number: 8178910Abstract: The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET.Type: GrantFiled: August 31, 2010Date of Patent: May 15, 2012Assignee: Rohm Co., Ltd.Inventor: Toshio Nakajima
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Publication number: 20120112286Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.Type: ApplicationFiled: November 3, 2011Publication date: May 10, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
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Publication number: 20120112823Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.Type: ApplicationFiled: November 3, 2011Publication date: May 10, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Andrew Marshall
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Publication number: 20120098058Abstract: A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Inventors: Lei Zhang, Tiesheng Li
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Publication number: 20120098061Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Inventor: Fred Session
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Publication number: 20120091516Abstract: Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled trenches in the termination regions are arranged with an orientation that is either parallel or perpendicular to the trenches in the active device drift region. The Voltage termination structures can also include capacitively segmented trench structures having dielectric lined regions filled with conducting material and completely surrounded by a silicon mesa region. The Voltage termination structures can further include continuous regions composed entirely of an electrically insulating layer extending a finite distance vertically from the device surface.Type: ApplicationFiled: April 11, 2011Publication date: April 19, 2012Inventors: Robert Kuo-Chang Yang, Sunglyong Kim, Joseph A. Yedinak
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Publication number: 20120092068Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.Type: ApplicationFiled: November 23, 2011Publication date: April 19, 2012Inventor: Scott C. McLeod
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Publication number: 20120091517Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.Type: ApplicationFiled: September 14, 2011Publication date: April 19, 2012Inventor: Danielle A. Thomas
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Publication number: 20120091529Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen (Albert) Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8159015Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.Type: GrantFiled: January 13, 2010Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni
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Publication number: 20120086062Abstract: In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other such that when the MOSFET is made to assume an OFF state, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity.Type: ApplicationFiled: October 11, 2011Publication date: April 12, 2012Inventors: KYOICHI HOSOKAWA, Ryotaro Kudo, Toshio Nagasawa, Koji Tateno
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Publication number: 20120087460Abstract: A semiconductor device comprising a circuit including a plurality of thin film transistors and at least one diode (D2a), wherein: the plurality of thin film transistors have the same conductivity type; when the conductivity type of the plurality of thin film transistors is an N type, a cathode-side electrode of the diode (D2a) is connected to a line (550) connected to a gate of a selected one of the plurality of thin film transistors; when the conductivity type of the plurality of thin film transistors, an anode-side electrode of the diode is connected to a line (550) connected to a gate of a selected one of the plurality of thin film transistors; and another diode arranged so that a current flow direction thereof is opposite to that of the diode (D2a) is not formed on the line (550). Thus, it is possible to suppress damage to a thin film transistor due to ESD while suppressing the increase in circuit scale from conventional techniques.Type: ApplicationFiled: June 9, 2010Publication date: April 12, 2012Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Moriwaki
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Publication number: 20120086060Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.Type: ApplicationFiled: October 5, 2011Publication date: April 12, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Koji Taniguchi
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Patent number: 8154085Abstract: A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a floating gate electrode layer located on the first gate insulating film, a first inter-gate insulating film located on the floating gate electrode layer, a control gate electrode layer located on the first inter-gate insulating layer, and a first low-resistance layer located on the control gate electrode layer. Each resistor has a second gate insulating film located on the semiconductor substrate, a first electrode layer located on the second gate insulating film, a second inter-gate insulating film located on the first electrode layer, a second electrode layer located on the second inter-gate insulating film, a second low-resistance layer located on the second electrode layer, and a contact plug connected to the second low-resistance layer.Type: GrantFiled: May 17, 2007Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Shigeru Ishibashi
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Publication number: 20120074478Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.Type: ApplicationFiled: June 28, 2011Publication date: March 29, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tatsuya Sugimachi
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Patent number: 8143162Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.Type: GrantFiled: July 10, 2009Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Yung-Cheng Lu, Hui-Lin Chang, Ting-Yu Shen, Hung Chun Tsai
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Publication number: 20120068239Abstract: A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.Type: ApplicationFiled: November 25, 2011Publication date: March 22, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jong Su KIM
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Publication number: 20120068269Abstract: This patent disclosure presents circuits, system, and method to produce an ideal memory cell and a method to produce a perfect PN junction without undesirable junction voltage and leakage current. These new inventions finally perfect the art to produce PN junction diode sixty years after PN junction diode was invented and the technology to produce an indestructible nonvolatile memory cell that is fast and small.Type: ApplicationFiled: September 14, 2011Publication date: March 22, 2012Inventor: Wen Lin
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Publication number: 20120068221Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.Type: ApplicationFiled: September 21, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko KITAGAWA
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Publication number: 20120062811Abstract: An object of the present invention is to provide a liquid crystal display device which allows a desirable storage capacitor to be ensured in a pixel without decreasing the aperture ratio in response to changes in frame frequency. In a liquid crystal display device including a pixel transistor and two capacitive elements using an oxide semiconductor material in each pixel, one of the capacitive elements comprises a light-transmitting material to improve the aperture ratio of the pixel. Furthermore, through the use of characteristics of the light-transmitting capacitive element, the size of the storage capacitor in the pixel is varied by adjusting the voltage value of a capacitance value in response to the frame frequency varied depending on images displayed.Type: ApplicationFiled: August 18, 2011Publication date: March 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Hiroyuki MIYAKE
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Publication number: 20120061740Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.Type: ApplicationFiled: November 22, 2011Publication date: March 15, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
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Patent number: 8133783Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.Type: GrantFiled: October 21, 2008Date of Patent: March 13, 2012Assignee: HVVi Semiconductors, Inc.Inventor: Bishnu P. Gogoi
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Layout method of semiconductor device with junction diode for preventing damage due to plasma charge
Patent number: 8133778Abstract: Provided is a layout method of junction diodes for preventing damage caused by plasma charge. The layout method includes operations of forming an active layer so as to form a plurality of active regions in a unit layout pattern; forming a gate layer so as to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed so as to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region so as to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions so as to form a junction diode in at least one active region between the first and second conductive type active regions.Type: GrantFiled: March 12, 2008Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Young Kim, Jong-Hak Won -
Publication number: 20120056303Abstract: A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions.Type: ApplicationFiled: September 1, 2011Publication date: March 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Young-Jin Cho
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Patent number: 8129772Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.Type: GrantFiled: June 15, 2010Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Publication number: 20120049323Abstract: The present disclosure is directed to an integrated circuit having a substrate and a first and a second interconnect structure over the substrate. Each interconnect structure has a first conductive layer over the substrate and a second conductive layer over the first conductive layer. The integrated circuit also includes a thin film resistor over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.Inventors: Hui Chong Vince Ng, Olivier Le Neel, Calvin Leung
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Publication number: 20120049260Abstract: A semiconductor device includes a MOS capacitor including a gate, a source, and a drain, a cylinder capacitor including a top electrode, a dielectric layer, and a bottom electrode, and a metal interconnection that connects the gate to the bottom electrode.Type: ApplicationFiled: August 25, 2011Publication date: March 1, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hyun Seok KIM, Jun Ho LEE, Boo Ho JUNG, Sun Ki CHO, Yang Hee KIM, Young Won KIM
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Publication number: 20120049291Abstract: In sophisticated semiconductor devices, resistors may be provided together with high-k metal gate electrode structures by using a polycrystalline silicon material without requiring a deterioration of the crystalline nature and thus conductivity of a conductive metal-containing cap material that is used in combination with the high-k dielectric gate material. In this manner, superior uniformity of the resistance values may be obtained, while at the same time reducing the overall process complexity.Type: ApplicationFiled: July 18, 2011Publication date: March 1, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Thilo Scheiper, Steven Langdon
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Patent number: 8125049Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.Type: GrantFiled: November 16, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper