In Combination With Diode, Resistor, Or Capacitor (epo) Patents (Class 257/E27.016)
  • SWITCH CIRCUIT USING LDMOS ELEMENT
    Publication number: 20120241859
    Abstract: The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (VGS) of the LDMOS device may be stably controlled through a current source and resistances, the characteristics of a switch may be maintained regardless of the voltages of both terminals (A and B) by using an N-type LDMOS and a P-type LDMOS in a complementary manner, and the current generated by the current source is offset inside the switch without flowing to the outside of the switch.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 27, 2012
    Applicant: SILICON WORKS CO., LTD
    Inventors: Young-Jin WOO, Kong-Soon Park, Young-Sik Kim
  • LOW LOSS SWITCHED CAPACITOR
    Publication number: 20120242395
    Abstract: An integrated circuit including a capacitor bank is disclosed. The capacitor bank includes one or more cells. Each cell may include two capacitors in series and a transistor in parallel with one of the capacitors. The transistor switches a capacitance of the parallel capacitor in or out of a larger circuit.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventor: Yongwang Ding
  • Semiconductor device with resistive element
    Patent number: 8269312
    Abstract: A semiconductor device according to an aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a first insulator embedded in the semiconductor layer with a thickness larger than the thickness of the insulating film, and a resistive element formed on the first insulator. A semiconductor device according to another aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a resistive element formed on the insulating film, and a floating region formed on a portion of the semiconductor layer opposed to the resistive element through the insulating film and electrically floating from a periphery thereof.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: September 18, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
    Patent number: 8269280
    Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: September 18, 2012
    Assignee: LSI Corporation
    Inventor: Jau-Wen Chen
  • METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20120228677
    Abstract: A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Inventors: Fujio Masuoka, Nozomu Harada
  • SEMICONDUCTOR DEVICE
    Publication number: 20120228690
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 13, 2012
    Inventors: Satoshi MAEDA, Yasushi Sekine, Tetsuya Watanabe
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20120228686
    Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 13, 2012
    Inventors: Ayako INOUE, Kazuhiro Tsumura
  • SEMICONDUCTOR DEVICE WITH RESISTANCE CIRCUIT
    Publication number: 20120228719
    Abstract: Provided is a resistance circuit having a resistance element with high resistance and high accuracy. An insulating film such as a silicon nitride film is formed on the resistance element made of a thin film material whose thickness is reduced to 500 ? or smaller. The insulating film prevents passing through of the contact hole arranged on the resistance element during etching for forming the contact hole.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 13, 2012
    Inventor: Hirofumi HARADA
  • SEMICONDUCTOR DEVICE
    Publication number: 20120228632
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.
    Type: Application
    Filed: September 7, 2011
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiharu Takada, Kentaro Ikeda
  • Protection of integrated circuit gates during metallization processes
    Patent number: 8264043
    Abstract: In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: September 11, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sanjay Rekhi, Nagendra Cherukupalli, Paul D. Keswick
  • SEMICONDUCTOR DEVICE
    Publication number: 20120223375
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Inventors: Satoshi MAEDA, Yasushi SEKINE, Tetsuya WATANABE
  • BIDIRECTIONAL SWITCH
    Publication number: 20120217542
    Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer. The semiconductor element includes a first ohmic electrode and a second ohmic electrode, and a first gate electrode and a second gate electrode, which are sequentially formed on the first ohmic electrode between the first ohmic electrode and the second ohmic electrode. The substrate potential stabilizer sets a potential of the substrate lower than higher one of a potential of the first ohmic electrode or a potential of the second ohmic electrode.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 30, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: Tatsuo MORITA
  • SEMICONDUCTOR DEVICE LIMITING ELECTRICAL DISCHARGE OF CHARGE
    Publication number: 20120217581
    Abstract: A semiconductor device includes a source region embedded in the surface of the second semiconductor region, a drain region embedded in the surface of the first semiconductor region separated from the second semiconductor region, a gate electrode located on the second semiconductor region, an insulation film located on the first semiconductor region between the second semiconductor region and the drain region, a voltage dividing element dividing the voltage between the gate electrode and the drain region, and a charge transfer limiting element limiting transfer of charge from the voltage dividing element to the drain region.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 30, 2012
    Applicant: Sanken Electric Co., Ltd.
    Inventor: Satoshi KONDOU
  • INTEGRATED CIRCUITS WITH RESISTORS AND METHODS OF FORMING THE SAME
    Publication number: 20120217586
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 30, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH
  • Semiconductor device including a capacitor electrically connected to a vertical pillar transistor
    Patent number: 8247856
    Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Jung Kim, Yong-Chul Oh, Jae-Man Yoon, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim
  • Device and Associated Semiconductor Package for Limiting Drain-Source Voltage of Transformer-Coupled Push Pull Power Conversion Circuit
    Publication number: 20120205745
    Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX +½Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Inventor: Sanjay Havanur
  • Semiconductor Device with Low-Conducting Field-controlling Element
    Publication number: 20120205667
    Abstract: A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region, and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer having a sheet resistance between approximately 103 Ohms per square and approximately 107 Ohms per square. During direct current and/or low frequency operation, the field-controlling element can behave similar to a metal electrode. However, during high frequency operation, the field-controlling element can behave similar to an insulator.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 16, 2012
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Lateral Power MOSFET With Integrated Schottky Diode
    Publication number: 20120205740
    Abstract: A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 16, 2012
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, David N. Okada, Gary Dashney, David A. Shumate
  • SEMICONDUCTOR MODULE
    Publication number: 20120206196
    Abstract: A PFC module includes: a diode bridge having first and second diodes in the upper arm, and third and fourth diodes in the lower arm; and first and second switching elements for power factor correction. The first and second diodes are Schottky barrier diodes formed by using a wide bandgap semiconductor. The third and fourth diodes, and the first and second switching elements are Schottky barrier diodes and switching elements respectively formed by using silicon.
    Type: Application
    Filed: November 17, 2011
    Publication date: August 16, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masahiro KATO, Shinya NAKAGAWA
  • Method of manufacturing semiconductor device having integrated MOSFET and Schottky diode
    Patent number: 8241978
    Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: August 14, 2012
    Assignee: Anpec Electronics Corporation
    Inventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
  • NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE FOR SUPPRESSING DETERIORATION IN JUNCTION BREAKDOWN VOLTAGE AND SURFACE BREAKDOWN VOLTAGE OF TRANSISTOR
    Publication number: 20120199896
    Abstract: According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region.
    Type: Application
    Filed: September 16, 2011
    Publication date: August 9, 2012
    Inventors: Mitsuhiro NOGUCHI, Hiroyuki Kutsukake, Masato Endo
  • Semiconductor device
    Patent number: 8237223
    Abstract: A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 7, 2012
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Ta-Chuan Kuo
  • Thin-Film Transistor Array Substrate and Method of Fabricating the Same
    Publication number: 20120193624
    Abstract: A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.
    Type: Application
    Filed: August 26, 2011
    Publication date: August 2, 2012
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventor: Chun-Gi You
  • POWER SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20120193701
    Abstract: A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.
    Type: Application
    Filed: May 5, 2011
    Publication date: August 2, 2012
    Inventor: Wei-Chieh Lin
  • Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors
    Publication number: 20120193695
    Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Inventors: Yan Xun Xue, Anup Bhalla, Jun Lu
  • ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20120193629
    Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.
    Type: Application
    Filed: April 4, 2012
    Publication date: August 2, 2012
    Applicant: AU OPTRONICS CORP.
    Inventors: Hsiang-Lin LIN, Ching-Huan LIN, Chih-Hung SHIH, Wei-Ming HUANG
  • Semiconductor device including field effect transistor with reduced electric field concentration
    Patent number: 8232609
    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
  • Gated diode structure and method including relaxed liner
    Patent number: 8232603
    Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha
  • Lateral epitaxial grown SOI in deep trench structures and methods of manufacture
    Patent number: 8232163
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Brian Messenger, Karen A. Nummy, Ravi M. Todi
  • EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
    Publication number: 20120187493
    Abstract: An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi
  • Integrated circuit resistive devices including multiple interconnected resistance layers
    Patent number: 8227897
    Abstract: A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jongwon Kim
  • Systems and methods for a continuous-well decoupling capacitor
    Patent number: 8227846
    Abstract: A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Andrew E. Carlson
  • SEMICONDUCTOR DEVICE
    Publication number: 20120181611
    Abstract: The invention provides a semiconductor device including an ESD protection circuit with a high ESD protection characteristic. An RC timer included discharge portion including an RC timer formed by a resistor element and a capacitor element and a PLDMOS transistor is formed so as to turn on only when a surge voltage due to static electricity is applied. Furthermore, a noise prevention portion including first and second NMOS off transistors of which the source electrode and the drain electrode are connected is formed. The source electrode of the PLDMOS transistor of the RC timer included discharge portion is connected to a power supply line. The drain electrode of the PLDMOS transistor and the drain electrode of the first NMOS off transistor are connected. The source electrode of the second NMOS off transistor is connected to a ground line.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Applicant: Semiconductor Components Industries, LLC
    Inventor: Kazumasa AKAI
  • FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
    Publication number: 20120181543
    Abstract: Disclosed are a flexible semiconductor device and manufacturing method therefor whereby the capacitances of capacitor parts of semiconductor elements and the like can be increased while decreasing parasitic capacitances that arise between multilevel interconnections. The disclosed flexible semiconductor device is provided with an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element comprises: a semiconductor layer formed on the top surface of the insulating film; a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer; and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer.
    Type: Application
    Filed: April 14, 2011
    Publication date: July 19, 2012
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Semiconductor device with embedded low-K metallization
    Patent number: 8222103
    Abstract: Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3).
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: July 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser
  • Semiconductor structure
    Patent number: 8222678
    Abstract: A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Method for making self aligning pillar memory cell device
    Patent number: 8222071
    Abstract: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: July 17, 2012
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Organic Light-Emitting Display and Method of Manufacturing the Same
    Publication number: 20120175615
    Abstract: In an organic light-emitting display having superior image quality and device reliability, and a related method of manufacturing the organic light-emitting display, the organic light-emitting display comprises: a gate electrode formed on a substrate; an interlayer insulating film formed on the substrate so as to cover the gate electrode; and a transparent electrode formed on the interlayer insulating film. The interlayer insulating film comprises multiple layers having different refractive indices.
    Type: Application
    Filed: June 14, 2011
    Publication date: July 12, 2012
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Chun-Gi You, Joon-Hoo Choi
  • Monolithically-Integrated New Dual Surge Protective Device and Its Fabrication Method
    Publication number: 20120175704
    Abstract: A monolithically-integrated dual surge protective device and its fabrication method are disclosed. The exemplary dual surge protective device includes a LDMOS device and a diode assembly which is consisted. of multiple diodes series-wound on back-to-back basis and whose one end is connected to drain electrode of the LDMOS device and the other-end is connected to gate electrode of the LDMOS device. The diode assembly can be fabricated directly in the gate electrode area of the LDMOS device after fabrication of the LDMOS device is completed. The protective device is equivalent to combination of diodes and LDMOS in respect to operating principles and structures, with the advantage of enhanced effect of surge prevention and cost reduction of surge device as it can be integrated into a chip.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 12, 2012
    Applicant: NORTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventor: Yanfeng Jiang
  • System and Method for Manufacturing a Temperature Difference Sensor
    Publication number: 20120175687
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Application
    Filed: March 21, 2012
    Publication date: July 12, 2012
    Applicant: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices
    Publication number: 20120175635
    Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Application
    Filed: October 17, 2011
    Publication date: July 12, 2012
    Applicant: Infineon Technologies Austria AG
    Inventors: Rolf Weis, Franz Hirler, Matthias Stecher, Armin Willmeroth, Gerald Deboy, Martin Feldtkeller
  • Bi-directional DMOS with common drain
    Patent number: 8217453
    Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: July 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer P. Pendharkar
  • Power semiconductor device
    Patent number: 8217487
    Abstract: Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: July 10, 2012
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Yongcheol Choi, Chang-Ki Jeon, Minsuk Kim, Donghwan Kim
  • PROTECTION ELEMENT AND SEMICONDUCTOR DEVICE HAVING THE PROTECTION ELEMENT
    Publication number: 20120168867
    Abstract: Disclosed herein is a protection element for protecting a circuit element. The protection element includes source and drain areas created in a semiconductor layer, a gate created on the semiconductor layer, sandwiching a gate insulation film between the gate and the semiconductor layer, a source electrode connected to the surface of the source area and electrically connected to the ground, a drain electrode connected to the surface of the drain area and used for receiving a surge input, and a diode connected between the source electrode and the gate.
    Type: Application
    Filed: December 21, 2011
    Publication date: July 5, 2012
    Applicant: Sony Corporation
    Inventor: Takaaki TATSUMI
  • POWER DEVICE PACKAGE STRUCTURE
    Publication number: 20120168839
    Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.
    Type: Application
    Filed: July 14, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiin-Shing Perng, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang
  • SEMICONDUCTOR DEVICE FOR PREVENTING PLASMA INDUCED DAMAGE AND LAYOUT THEREOF
    Publication number: 20120168870
    Abstract: A semiconductor device includes a diode having a first terminal connected to a first-conductivity-type well, and a second-conductivity-type MOS transistor having a first junction and a gate connected to a second terminal of the diode, and a second junction connected to a first power supply voltage terminal.
    Type: Application
    Filed: May 5, 2011
    Publication date: July 5, 2012
    Inventor: Jong-Su KIM
  • SEMICONDUCTOR DEVICE HAVING A RESISTOR AND METHODS OF FORMING THE SAME
    Publication number: 20120168871
    Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.
    Type: Application
    Filed: March 6, 2012
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinhyun Shin, Minchul Kim, Seong Soon Cho, Seungwook Choi
  • Resistance changing device and method for fabricating the same
    Patent number: 8212232
    Abstract: A resistance changing device includes a resistive layer of a hetero structure interposed between a lower electrode and an upper electrode, and including a plurality of resistive material layers, each having a different resistivity, stacked therein, wherein resistivities of the resistive material layers decrease from the lower electrode toward the upper electrode. Since the resistive layer has a hetero structure in which a plurality of resistive material layers, each having a different resistivity, are stacked in such a manner that the resistivity decreases as it goes from the lower electrode to the upper electrode, it is possible to improve the distributions of the set/reset voltage and the set/reset current, while reducing a reset current of a resistance changing device at the same time.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: July 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yu-Jin Lee
  • SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20120161145
    Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • ROBUST ESD CELL WITH ADJUSTABLE HOLDING VOLTAGE FOR ADVANCED ANALOG TECHNOLOGIES
    Publication number: 20120161232
    Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Farzan Farbiz, Akram Salman