Abstract: The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.

Abstract: Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.

Abstract: A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.

Abstract: A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted into the substrate, and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness of less than about 100 ?, and the second side having a thickness equal to or greater than 125 ?.

Abstract: Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69?) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94?) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94?) may be external to the transistor (69, 69?), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69?-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.

Abstract: Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.

Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.

Abstract: A switching device has an input node, an output node, and a control node. The device includes: a substrate having a first side and a second side with a ground plane on the first side of the substrate and a mesa on the second side of the substrate. The mesa is made of a normally-conductive semiconductor material, and an isolation region substantially surrounds the mesa. A field effect transistor (FET) is on the mesa. The FET has an input terminal connected to the input node, an output terminal connected to the output node, and a gate. A capacitor is connected in series between the output terminal of the FET and the gate, and a resistor is connected in series between the control node and the gate. A gate electrode is directly connected to the gate. The gate electrode is disposed substantially entirely on the mesa.

Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.

Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate.

Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate.

Abstract: Disclosed is a display device substrate and a display device in which a peripheral circuit is provided in a frame region that can achieve a higher aperture ratio while suppressing the production cost. The display device substrate includes a peripheral circuit provided in a frame region, a first pixel auxiliary capacitance, and a thin film transistor. The first pixel auxiliary capacitance includes an upper electrode and a lower electrode. The peripheral circuit includes wirings. The thin film transistor includes a gate electrode. The upper electrode and the lower electrode are disposed above the gate electrode, and formed of the same material as the wirings.

Abstract: A test system tests a semiconductor integrated circuit. The semiconductor integrated circuit including a signal terminal to and from a signal is input and output, an RF circuit which processes an RF signal, and a capacitor which is connected between the signal terminal and the RF circuit. The test system has a probe which applies a test signal to the signal terminal and a tester which tests the RF circuit. Before the RF circuit is tested, with the probe and the signal terminal in contact with each other, the tester determines whether the probe and the signal terminal are in a conductive state.

Abstract: In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer.

Abstract: There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction.

Abstract: A movable substrate is placed over a bottom substrate where both substrates contain Coulomb islands. The Coulomb islands can be adjusted in charge and are used to develop a force between two opposing Coulomb islands. Information from sensors is applied to a control unit to control the movement of the movable substrate. Coulomb islands are formed in the juxtaposed edges of a first substrate and second substrate, respectively. The islands generate edge Coulomb forces. These edge Coulomb forces can be used to detach, repel, move, attract and reattach the edges of substrates into new configurations. One possibility is to combine a plurality of individual substrates into one large planar substrate.

Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

Abstract: A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the first contact and is formed in at least a single interconnect layer; a second electro-conductive pattern located on the second contact so as to be opposed with the first electro-conductive pattern; and an interconnect formed in an upper interconnect layer which is located above the first electro-conductive pattern and the second electro-conductive pattern, so as to be located in a region above the first electro-conductive pattern and the second electro-conductive pattern.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.

Abstract: A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.

Abstract: A vertical transistor includes a gate isolating layer flanking a stack of a source layer, a resilient active unit and a drain layer, and a gate layer formed on the gate isolating layer. The active unit includes an active layer formed between first and second barrier layers each having a thickness ranging from 4 nm to 40 nm. When an input voltage including a DC component and a ripple component is applied to the source layer, the active unit periodically vibrates as a result of the ripple component of the input voltage such that an induced AC current is generated based on a control voltage applied to the gate layer to flow to the drain layer. The induced AC current flowing to the drain layer serves as an AC output generated by the vertical transistor based on the input voltage. A method of enabling a vertical transistor to generate an AC output is also disclosed.

Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

Abstract: An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

Abstract: An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Abstract: A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.

Abstract: A power switch with active snubber. In accordance with a first embodiment, an electronic circuit includes a first power semiconductor device and a second power semiconductor device coupled to the first power semiconductor device. The second power semiconductor device is configured to oppose ringing of the first power semiconductor device.

Abstract: A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.

Abstract: An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers.

Abstract: A detection device and system are provided. The detection device includes a detection capacitor and a Field Effect Transistor (FET). The detection capacitor has a reactive material layer reacting to a specific functional group in a fluid, and first and second electrodes disposed on the both surfaces of an insulating layer, and the FET has a source electrode connected with the second electrode, a gate electrode connected with the first electrode, and a drain electrode. Here, the insulating layer of the detection capacitor is thicker than a gate insulating layer of the FET.

Abstract: A method of manufacturing a semiconductor memory device includes forming a first capacitor using a metal oxide semiconductor (MOS) transistor, forming a second capacitor being a pillar type corresponding to a cell capacitor formed in a cell region, and forming a third capacitor over the first and the second capacitors

Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

Abstract: A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

Abstract: In semiconductor devices comprising sophisticated high-k metal gate electrode structures, resistors may be formed on the basis of a semiconductor material by increasing the sheet resistance of a conductive metal-containing cap material on the basis of an implantation process. Consequently, any complex etch techniques for removing the conductive cap material may be avoided.

Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.

Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

Abstract: A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.

Abstract: Non-direct bond copper isolated lateral wide band gap semiconductor devices are provided. One semiconductor device includes a heat sink, a buffer layer directly overlying the heat sink, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Another semiconductor device includes a heat sink, a substrate directly overlying the heat sink, a buffer layer directly overlying the substrate, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Being formed of a group-III nitride enables the various epitaxial layers to be electrically isolated from their respective heat sinks.

Abstract: A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 ?m or more.

Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

Abstract: A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A radio frequency (RF) semiconductor device includes a semiconductor substrate, a resistor film formed at one area of the semiconductor substrate, a first metal layer formed on the semiconductor substrate, a dielectric layer formed at least on the lower electrode film, a second metal layer formed on the dielectric layer, a first insulating layer having a first pad via connected with the first metal layer, a capacitor via connected with the second metal layer, and an inductor via connected with the first or second metal layer. a third metal layer includes filling parts that fill the capacitor via and the inductor via, respectively, and a second circuit line. A second insulating layer is formed on the first insulating layer to have a second pad via connected with the first pad via. A bonding pad is formed at the first and second pad vias.

Abstract: In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures.