Abstract: There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip.

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

Abstract: Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.

Abstract: An electrostatic protection element is disposed commonly to a plurality of output circuits along a long side of an output circuit region. More preferably, the electrostatic protection element should be disposed between a Pch region and an Nch region of an output circuit.

Abstract: In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized.

Abstract: Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.? doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.? doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.? doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: A semiconductor light receiving device includes a plurality of photodiode units, each of which is configured to convert a received light into an electric signal; and a separating unit configured to electrically separates the plurality of photodiode units from each other. The impurity concentration of a surface portion of the separating unit is equal to or lower than a first concentration. The first concentration is a concentration at which the light receiving sensitivity of the separating unit to light is substantially equal to the light receiving sensitivity of each of the plurality of photodiode units of the light. A wavelength of the light is equal to or longer than that of blue-violet light.

Abstract: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield (62) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

Abstract: A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply potentials: two supplied to the sources of the field-effect transistors, one supplied to the substrate, and one supplied to the well. An unwanted pair of parasitic bipolar transistors are formed in association with the field-effect transistors. An intentionally formed bipolar transistor operates in series with one of the unwanted parasitic transistors and as a current mirror for the other unwanted parasitic transistor, limiting the flow of unwanted current through the parasitic bipolar transistors.

Abstract: A CMOS transistor comprises a substrate with a gate electrode arranged thereon between source and drain regions. A capacitor is provided on the gate electrode and a voltage applied to the gate electrode is dropped across a stack, including the gate electrode and the capacitor.

Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.

Abstract: In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.

Abstract: In an ESD protecting element, a plurality of source regions and a plurality of ballast resistor regions are formed. A drain region is formed at a region which is in contact with a channel region in the ballast resistor region, and an n+ type diffusion region is formed at a region isolated from the drain region via an STI region. A third contact is provided on the drain region, first and second contacts are formed on the n+ type diffusion region, and the first contact is connected to a pad. The second contact is coupled to the third contact by a metal wire. The first and second contacts are laid out along the widthwise direction of a gate.