Abstract: A fault protection circuit for an alternator is provided for preventing faults such as a prolonged full-field condition in the alternator. The fault protection circuit includes a safety switch that is opened when the alternator output voltage becomes too high, as may occur during a full-field condition caused by an electrical short, or when some other fault is detected within the alternator. The opening of this safety switch disconnects a supply voltage feeding an excitation current control switch. The excitation current control switch normally adjusts an excitation current provided to a rotor in the alternator, in order to regulate a voltage output from the alternator. By providing a safety switch that disconnects the supply voltage for the rotor excitation in the alternator, the alternator output voltage may be prevented from reaching excessive levels that may damage devices in an electrical system and a battery coupled to the alternator.

Abstract: The present invention relates to the field of radio frequency identification, in particular to a temperature measurement and calibration circuit and a passive radio frequency identification tag. Meanwhile, the present invention further relates to a method for performing temperature measurement by using the tag. The temperature measurement and calibration circuit of the tag generates an upper reference voltage value limit and a lower reference voltage value limit, which do not change with temperature, then calibrates the upper reference voltage value limit and the lower reference voltage value limit to a uniform upper voltage value limit and a uniform lower voltage value limit, and eliminates the problem of different reference voltages of tags due to the power supply voltage fluctuation and process deviation. Meanwhile, a temperature measurement voltage generator circuit of the tag generates a calibration voltage value under a uniform calibration temperature.

Abstract: A fault protection circuit for an alternator is provided for preventing faults such as a prolonged full-field condition in the alternator. The fault protection circuit includes a safety switch that is opened when the alternator output voltage becomes too high, as may occur during a full-field condition caused by an electrical short, or when some other fault is detected within the alternator. The opening of this safety switch disconnects a supply voltage feeding an excitation current control switch. The excitation current control switch normally adjusts an excitation current provided to a rotor in the alternator, in order to regulate a voltage output from the alternator. By providing a safety switch that disconnects the supply voltage for the rotor excitation in the alternator, the alternator output voltage may be prevented from reaching excessive levels that may damage devices in an electrical system and a battery coupled to the alternator.

Abstract: A semiconductor device and a power converter using it wherein a switching power device and a flywheel diode are connected in series, the flywheel diode includes a region having a Schottky junction to operate as a Schottky diode and a region having a pn junction to operate as a pn diode and control operation is performed such that when current flows forwardly through the flywheel diode, the pn diode operates and when the flywheel diode recovers backwardly, the Schottky diode operates mainly.

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract: An object is to provide a semiconductor device which includes a memory cell capable of holding accurate data even when the data is multilevel data. The semiconductor device includes a memory cell holding data in a node to which one of a source and a drain of a transistor whose channel region is formed from an oxide semiconductor. Note that the value of off-state current (leakage current) of the transistor is extremely small. Thus, after being set to have a predetermined value, the potential of the node can be kept constant or substantially constant by turning the transistor off. In this manner, accurate data can be stored in the memory cell.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region.

Abstract: An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.

Abstract: Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

Abstract: A semiconductor device has a source region, a channel region and a drain region formed in order along a surface of a substrate, a vertical type bipolar transistor formed from the source region below the substrate, a base contact region of the vertical type bipolar transistor, a buried layer connected to the vertical type bipolar transistor, a buried contact layer which electrically conducts the drain region and the buried layer and a drift region formed between the drain region and the channel region, which has the same conductive type as that of the drain region and has impurity concentration less than that of the drain region.

Abstract: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield (62) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

Abstract: An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.