Vertical Bipolar Transistor Only (epo) Patents (Class 257/E27.055)
  • Patent number: 10686037
    Abstract: A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, and an isolation structure. The engineered layer is surrounding the insulating substrate. The semiconductor layer, which includes a first region and a second region,. is formed over the engineered layer. The isolation structure is formed in the semiconductor layer and located between the first region and the second region. A first transistor and a second transistor are formed in the first region and the second region respectively.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Francois Hebert
  • Patent number: 9006833
    Abstract: A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman
  • Patent number: 8901713
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8866221
    Abstract: A drift layer of a super junction semiconductor device includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. The first and second portions are formed both in a cell area and in an edge area surrounding the cell area, wherein an on-state or forward current through the drift layer flows through the first portions in the cell area. At least one of the first and second portions other than the first portions in the cell area includes an auxiliary structure or contains auxiliary impurities to locally reduce the avalanche rate. Locally reducing the avalanche rate increases the total voltage blocking capability of the super junction semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans Weber, Hans-Joachim Schulze, Uwe Wahl
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8749024
    Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Marie Denison, Yongxi Zhang
  • Patent number: 8723295
    Abstract: The present invention makes it possible to inhibit an SOA (Safe Operating Area) in a vertical-type bipolar transistor from narrowing. A p-type base layer 150 includes a first peak, a second peak, and a third peak in an impurity profile in the thickness direction. The first peak is located on the topmost surface side of a semiconductor substrate 100. The second peak is located closer to the bottom face side of the semiconductor substrate 100 than the first peak and higher than the first peak. The third peak is located between the first peak and the second peak.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Fukui, Hiroaki Katou
  • Patent number: 8643056
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Kimura, Yasuto Sumi, Hiroshi Ohta, Hiroyuki Irifune
  • Patent number: 8643085
    Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Frank Pfirsch
  • Patent number: 8455975
    Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Publication number: 20120305985
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Applicant: Force Mos Technology Co. Ltd.
    Inventor: Fu-Yuan HSIEH
  • Patent number: 8247300
    Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Publication number: 20120098098
    Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 26, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer P. Pendharkar, Marie Denison, Yongxi Zhang
  • Publication number: 20120061721
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi KIMURA, Yasuto SUMI, Hiroshi OHTA, Hiroyuki IRIFUNE
  • Publication number: 20120037954
    Abstract: A semiconductor power device with trenched contact having improved equal potential ring (EPR) structures for device die size shrinkage and yield enhancement are disclosed. The invented semiconductor power device comprising a termination area including an equal potential ring (EPR) formed with EPR contact metal plug penetrating through an insulation layer covering top surface of epitaxial layer and extended downward into an epitaxial layer. To prevent the semiconductor power device from EPR damage induced by die pick-up nozzle at assembly stage in prior art, some preferred embodiments of the present invention without having EPR front metal.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 8097919
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P?N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P?N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 17, 2012
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 7939912
    Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: May 10, 2011
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, George I. Bourianoff
  • Patent number: 7888712
    Abstract: A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: February 15, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Mineo Miura
  • Patent number: 7872326
    Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: January 18, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Magistretti, Fabio Pellizzer, Augusto Benvenuti
  • Patent number: 7863709
    Abstract: Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: January 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Runzi Chang, Chien-Chuan Wei, Winston Lee, Peter Lee
  • Patent number: 7847373
    Abstract: A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 7, 2010
    Inventors: Agostino Pirovano, Augusto Benvenuti, Fabio Pellizzer, Giorgio Servalli
  • Patent number: 7846805
    Abstract: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: December 7, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Shaoqiang Zhang, Purakh Raj Verma, Sanford Chu
  • Patent number: 7842537
    Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Brian S. Doyle
  • Patent number: 7777255
    Abstract: A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 17, 2010
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics / Leibniz-Instut für innovative Mikroelektronik
    Inventors: Holger Rücker, Bernd Heinemann
  • Patent number: 7719087
    Abstract: A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 18, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Satoshi Suzuki
  • Patent number: 7683428
    Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jochen Beintner, Ramachandra Divakaruni
  • Patent number: 7615457
    Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti
  • Patent number: 7612430
    Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: November 3, 2009
    Assignee: Infineon Technologies AG
    Inventors: Martin Franosch, Thomas Meister, Herbert Schäfer, Reinhard Stengl, Konrad Wolf
  • Patent number: 7586130
    Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Takeshi Takagi
  • Patent number: 7566948
    Abstract: A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a relatively low p-doping level in a first region proximate to the collector and a relatively high p-doping level in a second region proximate to an emitter. Alternatively, the accelerating field can be derived from band gap grading, wherein the grade of band gap in the first region is greater than the grade of band gap in the second region, and the average band gap of the first region is lower than that of the second region.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: July 28, 2009
    Assignee: Kopin Corporation
    Inventors: Eric M. Rehder, Roger E. Welser, Charles R. Lutz
  • Patent number: 7566626
    Abstract: A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 28, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Mingwei Xu, Jamal Ramdani
  • Publication number: 20090121319
    Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.
    Type: Application
    Filed: September 9, 2008
    Publication date: May 14, 2009
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 7495312
    Abstract: A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base and emitter regions and of the buried collector region are, for each of the vertical bipolar transistors, selected to create an overlap between the base and emitter regions, and the buried collector region, as seen from above, wherein at least some of the overlaps are selected to be different.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Infineon Technologies AG
    Inventors: Patrick Algotsson, Hans Norström, Karin Andersson
  • Patent number: 7494854
    Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 24, 2009
    Assignee: Transpacific IP, Ltd.
    Inventors: Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7488662
    Abstract: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: February 10, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Shaoqiang Zhang, Purakh Raj Verma, Sanford Chu
  • Publication number: 20080315361
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted.
    Type: Application
    Filed: July 7, 2005
    Publication date: December 25, 2008
    Inventors: Godefridus Adrianus Maria Hurkx, Prabhat Agarwal, Erwin Hijzen, Raymond Josephus Engelbart Hueting
  • Publication number: 20080296675
    Abstract: The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Masamichi YANAGIDA
  • Publication number: 20080224174
    Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.
    Type: Application
    Filed: December 21, 2007
    Publication date: September 18, 2008
    Inventors: Kenji SASAKI, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
  • Patent number: 7425754
    Abstract: A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: September 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti
  • Publication number: 20080203379
    Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Michele Magistretti, Fabio Pellizzer, Augusto Benvenuti
  • Patent number: 7161230
    Abstract: An insulated gate bipolar transistor has a P-type collector region containing a P-type impurity such as boron. A relatively thin N-type buffer region containing arsenic in a relatively high concentration is formed on the collector region via an anti-diffusion region. The anti-diffusion region is provided in such a way that its thickness is the same as or slightly smaller than the distance over which the P-type impurity is diffused from the collector region toward the buffer region in a device fabrication process.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: January 9, 2007
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Katsuyuki Torii, Ryoji Takahashi
  • Patent number: 7075156
    Abstract: Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: July 11, 2006
    Assignee: Marvell International Ltd.
    Inventors: Choy Li, Xin-Yi Zhang
  • Patent number: 7067900
    Abstract: An IGBT has an N-type buffer region between a P-type collector region and a P-type base region. The buffer region includes arsenic as a N-type impurity. The buffer region is formed to have a relatively high impurity concentration of equal to or greater than 5×1017 cm-3 and a relatively small thickness of 2 to 10 ?m.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: June 27, 2006
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Katsuyuki Torii, Ryoji Takahashi
  • Patent number: RE40222
    Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: April 8, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardo Fragapane