Abstract: A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins. Also disclosed is a method for forming a FinFET device.

Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.

Abstract: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

Abstract: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

Abstract: A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and in which a selection transistor is formed to supply a predetermined voltage to the memory transistor. The second region of the substrate may have a higher impurity concentration than an entire region of the substrate other than the second region. Reduced area of the selection transistor can be realized with a shortened channel length, without a decreased threshold voltage.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: A multi-layer piezoelectric component includes a plurality of piezoelectric layers, a first inner electrode sheet, a second inner electrode sheet, a first outer electrode, and a second outer electrode. The piezoelectric layers are wound around an axis to form a laminar roll having first and second end faces transverse to the axis. The piezoelectric layers include at least one first layer and at least one second layer. Each of the first and second layers has opposite first and second edges respectively at the first and second end faces, and opposite inner and outer circumferential surfaces. The first and second inner electrode sheets respectively overlie the inner circumferential surfaces of the first and second layers. The first and second outer electrodes are respectively and electrically connected to the first and second inner electrode sheets.