Field-effect Transistor With Insulated Gate (epo) Patents (Class 257/E27.06)
  • Patent number: 10451444
    Abstract: An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for performing a comparison between an analog signal inputted from a detector for detecting rotation of a motor and the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; a resistance value variation circuit for varying the resistance value of the variable resistor; and a threshold value determination circuit for determining the threshold value based on a relationship between the resistance value and the comparator output.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 22, 2019
    Assignee: FANUC CORPORATION
    Inventors: Youhei Kondou, Keisuke Imai
  • Patent number: 10444041
    Abstract: An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for comparing an analog signal inputted from a detector for detecting rotation of a motor with the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; an A/D converter for converting the analog signal into a digital signal; a threshold value determination circuit for calculating a new threshold value using the digital signal; and a resistance value change circuit for changing a resistance value of the variable resistor, such that the calculated new threshold value is inputted from the voltage generation circuit to the comparator.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 15, 2019
    Assignee: FANUC CORPORATION
    Inventors: Youhei Kondou, Keisuke Imai
  • Patent number: 10367497
    Abstract: The present invention concerns a system comprising a multi-die power module composed of dies and a controller receiving plural consecutive input patterns for activating the dies of the multi-die power module, wherein the dies are grouped into plural groups of at least one die and in that the controller comprises: —means for outputting one gate to source signal for each group of at least one die, the rising edges and/or falling edges of at least one gate to source signal being iteratively time shifted from the rising edge and/or a falling edge of the other gate to source signals for other groups of dies.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 30, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Stefan Mollov, Jeffrey Ewanchuk
  • Patent number: 10283500
    Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 7, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael L. Fraser, Frank E. Danaher, Jason R. Fender
  • Patent number: 10230377
    Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 12, 2019
    Assignee: Tela Innovations, Inc.
    Inventor: Scott T. Becker
  • Patent number: 9819271
    Abstract: A power converter for converting input power to output power includes a first transformer circuit, a second transformer circuit, and balance circuitry. The first transformer circuit includes a first primary winding for receiving a first part of the input power and a first secondary winding for generating a first part of the output power. The second transformer circuit includes a second primary winding for receiving a second part of the input power and a second secondary winding for generating a second part of the output power. The balance circuitry is coupled to a first terminal of the first secondary winding and a second terminal of the second secondary winding, and operable for balancing the first and second parts of the output power by passing a signal between the first and second terminals. The first and second terminals have the same polarity.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 14, 2017
    Assignee: O2Micro, Inc.
    Inventors: Catalin Popovici, Alin Gherghescu, Laszlo Lipcsei
  • Patent number: 9761585
    Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 12, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sami Hyvonen, Jad B. Rizk, Frank O'Mahony
  • Patent number: 9666287
    Abstract: A voltage detector for detecting whether an input voltage is no lower than a predetermined threshold voltage, includes a reference voltage generator configured to generate a reference voltage, and a comparator configured to receive the input voltage and the reference voltage and to detect whether the input voltage is no lower than the threshold voltage that is determined by the reference voltage. Here, the reference voltage generator includes a first write MOS transistor, a second write MOS transistor, a first output MOS transistor and a second output MOS transistor each including a control gate and a floating gate.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 30, 2017
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yoshiro Yamaha, Satoshi Takehara
  • Patent number: 9501739
    Abstract: According to one embodiment, a neuron learning type integrated circuit device includes neuron cell units. Each of the neuron cell units includes synapse circuit units, and a soma circuit unit connected to the synapse circuit units. Each of the synapse circuit units includes a first transistor including a first terminal, a second terminal, and a first control terminal, a second transistor including a third terminal, a fourth terminal, and a second control terminal, a first condenser, one end of the first condenser being connected between the second and third terminals, and a control line connected to the first and second control terminals. The soma circuit unit includes a Zener diode including an input terminal and an output terminal, the input terminal being connected to the fourth terminal, and a second condenser, one end of the second condenser being connected between the fourth terminal and the input terminal.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Matsuoka, Hiroshi Nomura
  • Patent number: 9335775
    Abstract: Various embodiments include an integrated circuit (IC) structure having: a chip control logic; a chip power system connected with the chip control logic; and a voltage island connected with the chip control logic and the chip power system, the voltage island including: an interface component for interfacing with the chip power system and the chip control logic; a logic island connected with the interface component; and a voltage island power system connected with the interface component and the logic island, the voltage island power system independently controlling a voltage supplied to the logic island.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Donald W. Labrecque, Steffen A. Loeffler, Christopher P. Miller, Christopher Scoville
  • Patent number: 9035389
    Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wen, Wen-Shen Chou
  • Patent number: 9029954
    Abstract: A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a semiconductor substrate, a first gate insulating film having a first high-dielectric-constant insulating film containing a first metal for adjustment, and a first electrode formed on the first gate insulating film. A protrusion amount of one end of the first high-dielectric-constant insulating film on the first device isolation part is smaller than a protrusion amount of an end of the first gate electrode above the first device isolation part.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Tomohiro Fujita
  • Patent number: 9029951
    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama
  • Patent number: 9030618
    Abstract: A flexible display panel includes a first display region that is flat, second display regions located at both sides of the first display region and curved by a predetermined angle, a plurality of pixels formed in the first display region, and a plurality of pixels formed in the second display regions, Each of the plurality of pixels formed in the first display region and the second display regions includes a light-emitting diode and a driving thin-film transistor (TFT) connected to the light-emitting diode, the driving TFT supplying a driving current to the light-emitting diode. A size of the driving TFT varies for each of the plurality of pixels formed in the second display regions so that driving currents supplied by driving TFTs in the second display regions vary in one direction with respect to boundaries between the first display region and the second display regions.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Mu-Kyung Jeon
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Patent number: 9029256
    Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 9024392
    Abstract: Some embodiments relate to an integrated circuit including fin field effect transistors (FinFETs) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another. A gate dielectric layer is disposed over the first and second active fin regions. First and second gate electrodes are disposed over the first and second active fin regions, respectively. The first and second gate electrodes are also disposed over the gate dielectric layer. The first and second gate electrodes are electrically coupled together and are electrically separated from the first and second active fin regions by the gate dielectric layer. The first gate electrode is made of a first metal having a first workfunction, and the second gate electrode is made of a second metal having a second workfunction that differs from the first workfunction.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9018707
    Abstract: A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed symmetrically at both sides of the first gate and having a bent form; and a second transistor group including second transistors, wherein each of the second transistors includes a second gate, and a second source and a second drain disposed symmetrically at both sides of the second gate and having a bent form, wherein the first source and the first drain are bent in a direction opposite to a direction in which the second source and the second drain are bent.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventor: Min Gyu Koo
  • Patent number: 9012998
    Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: April 21, 2015
    Assignee: Cambridge Silicon Radio Ltd
    Inventors: Rainer Herberholz, Ludovic Oddoart, David Vigar
  • Patent number: 9013003
    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Patent number: 9006884
    Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 9000525
    Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chang Wen, Hsien-Cheng Wang, Chun-Kuang Chen
  • Patent number: 9000527
    Abstract: A semiconductor device is formed in which a first-type doped field effect transistor has a first gate stack that has an end portion with a second gate stack formed for a second-type, complementary doped field effect transistor. Lateral electrical contact is made between the first gate stack and the second gate stack. The lateral electrical contact provides an electrical shunt at the end of the first gate stack.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Apple Inc.
    Inventor: Date Jan Willem Noorlag
  • Patent number: 8994110
    Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichi Ishikawa
  • Patent number: 8987791
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Patent number: 8981489
    Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junjie Xiong, Yoon-Hae Kim, Hong-Seong Kang, Yoon-Seok Lee, You-Shin Choi
  • Patent number: 8981530
    Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8981377
    Abstract: A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: March 17, 2015
    Assignee: AU Optronics Corp.
    Inventor: Shou-Peng Weng
  • Patent number: 8975706
    Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer
  • Patent number: 8975704
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8975712
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 8975691
    Abstract: A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Great Power Semiconductor Corp.
    Inventor: Chun-Ying Yeh
  • Patent number: 8975699
    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama
  • Patent number: 8975674
    Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 10, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
  • Patent number: 8975710
    Abstract: By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Yuichiro Kitajima
  • Patent number: 8969974
    Abstract: The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active region of a first semiconductor material disposed on one of the semiconductor regions of the semiconductor substrate.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8969931
    Abstract: A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Joachim Knoch, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 8963240
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8963249
    Abstract: A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade
  • Patent number: 8963257
    Abstract: The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang
  • Patent number: 8952423
    Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Won Jeon, Hee-Sung Kang, Dae-Ho Yoon, Dal-Hee Lee, Suk-Joo Lee
  • Patent number: 8946829
    Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang, Chi-Wen Liu
  • Patent number: 8946709
    Abstract: A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Shuhei Nagatsuka
  • Patent number: 8941175
    Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Ke-Feng Lin, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang, Hsuan-Po Liao
  • Patent number: 8941183
    Abstract: There is provided a semiconductor device comprising, at least one SRAM cell, wherein the SRAM cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (Tinv) of a gate stack of the pass-gate transistor is different from Tinv of a gate stack of the pull-up transistor and Tinv of a gate stack of the pull-down transistor.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheong-Sik Yu, Choel-Hwyi Bae, Ju-Youn Kim, Chang-Min Hong
  • Patent number: 8941182
    Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Dominik Olligs, Jens Heinrich, Katrin Reiche
  • Patent number: 8933515
    Abstract: A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Huiming Bu, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Ali Khakifirooz, Devendra K. Sadana, Chun-Chen Yeh
  • Patent number: 8928067
    Abstract: A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method. The method includes implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8928033
    Abstract: A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction, a plurality of interconnection lines extending on the substrate in a second direction, a pad electrically connected to the plurality of interconnection lines and configured to apply an external voltage, a plurality of metal contacts electrically connecting the interconnection lines and the plurality of bit lines, and a plurality of bit line contacts that are in contact with the active region and electrically connect the plurality of bit lines and the active region, wherein a size of at least some of the bit line contacts and/or at least some of the metal contacts vary based on a distance of the respective bit line contact or the metal contact from the pad.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jong Kim, Jae-Hyeon Park, Sung-Hoon Bae, Jong-Wan Ma
  • Patent number: 8928091
    Abstract: Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles W. Koburger, III, Douglas C. LaTulipe, Jr.