Field-effect Transistor With Insulated Gate (epo) Patents (Class 257/E27.06)
  • Patent number: 11955081
    Abstract: A pixel includes: a storage capacitor connected between a first power supply voltage and a gate node; a first transistor including a gate electrode connected to the gate node; a second transistor to transfer a data signal to a source of the first transistor in response to a scan signal; a third transistor to diode-connect the first transistor in response to the scan signal, and including first and second sub-transistors serially connected between the gate node and a drain of the first transistor; a fourth transistor to transfer an initialization voltage to the gate node in response to an initialization signal, and including third and fourth sub-transistors serially connected between the gate node and the initialization voltage; and an organic light emitting diode including a cathode connected to a second power supply voltage. At least one of the second and fourth sub-transistors includes a bottom electrode.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: April 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyo Jin Lee, Joon-Chul Goh, Sangan Kwon, Hong Soo Kim, Hui Nam, Jin Young Roh, Sehyuk Park
  • Patent number: 11948939
    Abstract: An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kai-Chi Wu, Ching-Hung Kao, Meng-I Kang, Kuo-Fang Ting
  • Patent number: 11948937
    Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity-type; a bottom surface electrode to which a first potential is applied, the bottom surface electrode being provided on a bottom surface of the semiconductor base body; a first well of a second conductivity-type to which a second potential lower than the first potential is applied, the first well being provided on a top surface side of the semiconductor base body; a second well of the first conductivity-type provided in the first well; and an edge structure provided in the first well and configured to supply a third potential higher than the second potential to the second well.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 11948947
    Abstract: A display device includes pixel circuits disposed in a display area and a driving circuit disposed in the peripheral area. The driving circuit includes a first transistor and each pixel circuit includes a second transistor. The first transistor includes a first active pattern disposed on the substrate, a first gate insulation layer having a first outer portion disposed on the first active pattern, and a first gate electrode disposed on the first gate insulation layer. The second transistor includes a second active pattern disposed on the substrate, a second gate insulation layer having a second outer portion disposed on the second active pattern, and a second gate electrode disposed on the second gate insulation layer. The first outer portion doesn't overlap the first gate electrode and has a first width. The second outer portion doesn't overlap the second gate electrode and has a second width smaller than the first width.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang Soo Lee, Hyun Kim, Kap Soo Yoon, Su Jung Jung
  • Patent number: 11942515
    Abstract: A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongki Jung, Myungil Kang, Yoonhae Kim, Kwanheum Lee
  • Patent number: 11942540
    Abstract: A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 26, 2024
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Meng Wang, Yicheng Du, Hui Yu
  • Patent number: 11942514
    Abstract: The present application discloses a semiconductor device including a substrate; a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate; a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and wherein the first threshold voltage is different the second threshold voltage; a thickness of the first insulating stack is different from a thickness of the second insulating stack.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: March 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11943924
    Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 11942544
    Abstract: A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventor: Young Gwang Yoon
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11929370
    Abstract: Embodiments of the current disclosure to provide a display device which can reduce the number of intersections of scan lines and data lines. According to an embodiment of the disclosure, a display device comprises: a substrate; scan lines extending along a first direction; data lines extending along a second direction that intersect the first direction; a first switching element; a first pixel electrode connected to a first source electrode of the first switching element; a second switching element; and a second pixel electrode connected to a second source electrode of the second switching element. The first pixel electrode and the second pixel electrode are disposed along the second direction, and a first source electrode and a first drain electrode of the first switching element extend along the second direction in an area overlapping a first active layer of the first switching element.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong Young Lee, Kyung Ho Kim, Ki Won Park, Soo Hong Cheon
  • Patent number: 11925126
    Abstract: Technologies for tuning a resistance of tunnel junctions such as Josephson junctions are disclosed. In the illustrative embodiment, a Josephson junction is heated to 85 Celsius, and an electric field is applied to the Josephson junction. The heat and the electric field cause the resistance of the Josephson junction to increase. Monitoring the Josephson junction during the application of the electric field allows for the resistance of the Josephson junction to be adjusted to a particular value.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 5, 2024
    Assignee: THE UNIVERSITY OF CHICAGO
    Inventors: David Schuster, Andrew Oriani, Larry Chen
  • Patent number: 11916069
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 11910614
    Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
  • Patent number: 11901452
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Patent number: 11899311
    Abstract: A low-resolution image is displayed at high resolution and power consumption is reduced. Resolution is made higher by super-resolution processing. Then, display is performed with the luminance of a backlight controlled by local dimming after the super-resolution processing. By controlling the luminance of the backlight, power consumption can be reduced. Further, by performing the local dimming after the super-resolution processing, accurate display can be performed.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11894438
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
  • Patent number: 11895832
    Abstract: A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang, Chia-En Huang
  • Patent number: 11887937
    Abstract: An apparatus comprises a ground plane (2), an integrated circuit chip (1) disposed on the ground plane (2), the integrated circuit chip (1) comprising one or more electrically conductive layers (10) encircling a periphery of the integrated circuit chip (1), and a plurality of bondwires (9) electrically coupling the one or more electrically conductive layers (10) to the ground plane (2).
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: January 30, 2024
    Assignee: ams International AG
    Inventors: Benjamin Joseph Sheahan, Richard Jennings, Robert Allen Helmick, Marko Magerl, Christian Stockreiter
  • Patent number: 11889695
    Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Justin B. Dorhout, Indra V. Chary, Jun Fang, Matthew Park, Zhiqiang Xie, Scott D. Stull, Daniel Osterberg, Jason Reece, Jian Li
  • Patent number: 11881508
    Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Hyunchul Song, Sunjung Kim, Taegon Kim, Seong Hoon Jeong
  • Patent number: 11855202
    Abstract: A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ching Wu, Po-Jen Wang
  • Patent number: 11854898
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 11848336
    Abstract: An array substrate, a display panel, and a display apparatus are provided. The array substrate includes a substrate and a first thin-film transistor located on the substrate. In an embodiment, the first thin-film transistor includes a channel and a gate electrode. In an embodiment, an orthographic projection of the gate electrode on the substrate overlaps with an orthographic projection of the channel on the substrate. In an embodiment, the gate electrode comprises a first zone and a second zone that are arranged in a first direction. In an embodiment, the channel overlapping with the first zone in a direction perpendicular to the substrate has a total width W1 in a second direction perpendicular to the first direction, the channel overlapping with the second zone in a direction perpendicular to the substrate has a total width W2 in the second direction, and W1/W2?3.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 19, 2023
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Huiping Chai, Lijing Han, Guobing Wang
  • Patent number: 11844204
    Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: December 12, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Vinod Purayath, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11843033
    Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 12, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chen-Ying Wu, Abhishek Dube, Yi-Chiau Huang
  • Patent number: 11830946
    Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: November 28, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Shogo Mochizuki, Gen Tsutsui, Kangguo Cheng
  • Patent number: 11823954
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Patent number: 11824085
    Abstract: Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: November 21, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshihiro Imasaka, Kazuhiro Shimizu, Manabu Yoshino, Yuji Kawasaki
  • Patent number: 11817456
    Abstract: Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 14, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guillaume Alexandre Blin, Ambarish Roy, Seungwoo Jung
  • Patent number: 11817156
    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: November 14, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 11812617
    Abstract: A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sejie Takaki
  • Patent number: 11804460
    Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: October 31, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jiro Yota, Dogan Gunes
  • Patent number: 11798952
    Abstract: To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/?m or less and off-state current at 85° C. can be 100 aA/?m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/?m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11791389
    Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: October 17, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Kyle Bothe, Jia Guo, Jeremy Fisher, Scott Sheppard
  • Patent number: 11784187
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 11765473
    Abstract: An image sensor includes a plurality of pixel blocks and a connection unit. The plurality of pixel blocks includes: a diffusion unit to which an electric charge resulting from photoelectric conversion is transferred; and a transistor containing a source electrically connected with the diffusion unit. The connection unit is electrically connected with a drain of the transistor included in each of the plurality of pixel blocks.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: September 19, 2023
    Assignee: NIKON CORPORATION
    Inventors: Atsushi Komai, Yoshiyuki Watanabe, Osamu Saruwatari
  • Patent number: 11742237
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Patent number: 11735656
    Abstract: A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Touhidur Rahman, Shanghui Larry Tu
  • Patent number: 11728405
    Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Shih-Hao Lin
  • Patent number: 11729963
    Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyokyoung Kim, Jamin Koo, Jonghyeok Kim, Daeyoung Moon
  • Patent number: 11721746
    Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Patent number: 11723200
    Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang Min Kim, Jin Hyuk Kim, Jung Tae Sung, Joong Shik Shin, Sung Hyung Lee
  • Patent number: 11688780
    Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Stephen Cea
  • Patent number: 11686983
    Abstract: A display device is provided and includes display unit comprising common electrodes two dimensionally arrayed on substrate, drive signal lines configured to transmit drive signals for touch detection to common electrodes, and switch circuit comprising transistors connected to drive signal lines to select at least one common electrode; flexible substrate connected to substrate; pads at connections of flexible substrate and substrate; and touch detection circuit configured to transmit drive signals to common electrodes, wherein: transistors comprises: first transistor connected to first electrode of common electrodes via first wiring of first length; and second transistor connected to second electrode of common electrodes via second wiring of second length; channel width of first transistor is narrower than channel width of second transistor; drive signal lines are respectively connected to pads separated at two or more positions.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: June 27, 2023
    Assignee: Japan Display Inc.
    Inventor: Gen Koide
  • Patent number: 11682736
    Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chun Shen, Chi-Chung Jen, Ya-Chi Hung, Yu-Chu Lin, Wen-Chih Chiang
  • Patent number: 11676884
    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: June 13, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Michael Sutton, Sreenivasan K Koduri, Subhashish Mukherjee
  • Patent number: 11677028
    Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11670633
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: June 6, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 11670682
    Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: June 6, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Gilbert Dewey, Matthew V. Metz, Willy Rachmady, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Sean T. Ma, Jack T. Kavalieros