Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate. A conductive pad is arranged along a second side of the first substrate. A first through-substrate-via (TSV) physically contacts an interconnect of the first plurality of interconnects and a first surface of the conductive pad. A second plurality of interconnects are within a second ILD structure disposed on a second substrate. A second TSV extends from an interconnect of the second plurality of interconnects to through the second substrate. A conductive bump is arranged on a second surface of the conductive pad opposing the first surface. The second TSV has a greater width than the first TSV.

Abstract: A complementary field effect transistor (CFET) structure includes a vertical stack of first and second transistors, wherein the first transistor includes a first channel extending in a first direction from a first source/drain (S/D) region to a second S/D region through a gate extending in a second direction perpendicular to the first direction and the second transistor includes a second channel extending in the first direction from a third S/D region to a fourth S/D region through the gate. A first conductive trace extends in the first direction over the gate, a first via extends from the first S/D region to the first conductive trace and is aligned with the third S/D region along the second direction, a second via extends from the fourth S/D region to the first conductive trace, and the first via has a first height greater than a second height of the second via.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

Abstract: The present application provides a drive substrate and a display panel. The drive substrate includes: a substrate; a pixel driving circuit layer, arranged on the substrate; a first pad and a second pad spaced apart from the first pad, arranged on a side of the pixel driving circuit layer away from the substrate, and electrically connected to the pixel driving circuit layer. The drive substrate further includes an electrostatic protection line, the electrostatic protection line is spaced from the first pad, a side of the first pad facing the electrostatic protection line is arranged with a first toothed tip, and a side of the electrostatic protection line facing the first pad is arranged with a second toothed tip.

Abstract: An integrated circuit device includes; word lines extending in a first direction across a substrate and spaced apart in a second direction different from the first direction, bit lines extending on the word lines in the second direction and spaced apart in the first direction, a first contact plug arranged among the bitlines, contacting a first active region of the substrate, having a first width, and having a first dopant concentration, and a second contact plug arranged among the bitlines, contacting a second active region of the substrate, having a second width, and having a second dopant concentration less than the first dopant concentration.

Abstract: A radiation particle strike detection system is disclosed. The radiation particle strike detection system includes a radiation particle detector and a controller coupled to the radiation particle detector. The radiation particle detector is overlayed on at least one surface of a payload that is sensitive to interaction with radiation particles. The radiation particle detector is configured to undergo a change in state responsive to a radiation particle strike at a location on the radiation particle detector. The controller is configured to 1) monitor a state of the radiation particle detector; 2) detect a radiation particle strike on the radiation particle detector based on a change in state of the radiation particle detector; and 3) determine a location and time of the radiation particle strike on the radiation particle detector based on the change in state of the particle detector.

Abstract: A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.

Abstract: According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.

Abstract: A semiconductor structure includes a trunk portion and a branch portion. The trunk portion extends in a first direction. The branch portion is connected to the trunk portion. The branch portion includes a handle portion and a two-pronged portion. The handle portion is connected to the trunk portion and extends in a second direction. The second direction intersects the first direction. The two-pronged portion is connected to the handle portion. A line width of the handle portion is greater than a line width of the two-pronged portion.

Abstract: Various embodiments may provide an integrated circuit layout cell. The integrated circuit layout cell may include a doped region of a first conductivity type, a doped region of a second conductivity type opposite of the first conductivity type, and a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type. The integrated circuit cell may include a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal. The first controlled terminal and the second controlled terminal of the first transistor may include terminal regions of the second conductivity type formed within the further doped region of the first conductivity type. The integrated circuit cell may also include a second transistor.

Abstract: A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

Abstract: At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal configuration in a second metal layer of the memory cell. A third set of metal features are formed in the unidirectional horizontal configuration in a second metal layer of a functional cell for providing routing compatibility between the memory cell and the functional cell. The memory cell is placed adjacent to the functional cell for forming an integrated circuit device.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: An integrated circuit device includes: a pair of reference conductive lines arranged in parallel in a first direction in a first version logic cell and a pair of swap conductive lines arranged in parallel in a second version logic cell, wherein one reference conductive line and one swap conductive line in different wiring tracks of the pair of reference conductive lines and the pair of swap conductive lines have the same planar shape and the same length, and extend to intersect a cell boundary between the first version logic cell and the second version logic cell.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract: A static random access memory (SRAM) cell includes 1st and 2nd fins disposed on a substrate. A 1st pass gate transistor (1st PG) is embedded in the 1st fin. The 1st PG has a source region and a drain region disposed over the 1st and 2nd fins. A 1st gate structure (1st PG-G) is disposed over the 1st fin and between the source and drain regions. The 1st PG-G is electrically connected to a 1st word line. A 2nd pass gate transistor (2nd PG) is embedded in the 2nd fin. The 2nd PG has the same source and drain regions. A 2nd gate structure (2nd PG-G) is disposed over the 2nd fin and between the source and drain regions. The 2nd PG-G is electrically connected to a 2nd word line. A 1st CT pillar is disposed between the 1st PG-G and 2nd PG-G.

Abstract: A chip includes multiple first transistors in a first region and multiple second transistors in a second region. A gap between adjacent first transistors has a same width as a gap between adjacent second transistors. Gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.

Abstract: A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract: A column of a static random access memory (SRAM) array includes a first subarray including a first plurality of SRAM cells and a second subarray including a second plurality of SRAM cells. Each of the first and second plurality of SRAM cells includes first through fourth source active regions by which source regions of transistors thereof are formed. The column of the SRAM array includes a first bitline formed by the third source active regions of the first plurality of SRAM cells, a second bitline formed by the third source active regions of the second plurality of SRAM cells and spaced apart from the first bitline, and a third bitline formed by a metal layer extending over the third source active regions of the first and second plurality of SRAM cells and electrically connected to the second bitline but not to the first bitline.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.

Abstract: An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.

Abstract: An SRAM array is formed by a plurality of FinFETs formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region. From a first cross sectional view of the SRAM array, each fin line is of a rectangular shape. From a second cross sectional view of the SRAM array, the terminals of each fin line is of a tapered shape.

Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating film which covers the source/drain region and the gate electrode of the first transistor; and a first contact plug which is formed in the insulating film and is connected to the source/drain region or the gate electrode of the first transistor, wherein the first contact plug includes a first column section which extends in a thickness direction of the insulating film and is in contact with the source/drain region or the gate electrode of the first transistor, and a first flange section which juts out from an upper portion of the first column section in a direction parallel to a surface of the insulating film, and an upper surface of the first flange section is planarized.

Abstract: Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract: SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

Abstract: A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.

Abstract: The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arrange

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract: A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.