Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Abstract: A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.

Abstract: A method of manufacturing an integrated circuit device includes: doping a substrate with a first type dopant to form a well region; forming a first semiconductor fin and a second semiconductor fin wider than the first semiconductor fin over the well region; forming a first source/drain region of a second type dopant on the first semiconductor fin, the second type dopant is of a different conductivity type than the first type dopant; forming a second source/drain region of the first type dopant on the second semiconductor fin.

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

Abstract: A display device includes a scan line extending in a direction, a data line and a driving voltage line extending in another direction, a transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer, a second transistor electrically connected to the scan and data lines and including a second gate electrode and a second semiconductor layer, a first capacitor electrically connected to the first transistor and including first and second capacitor plates, and a second capacitor including a third capacitor plate electrically connected to the first transistor and a fourth capacitor plate electrically connected to the second transistor. The second capacitor plate includes a first hole overlapping the first capacitor plate, the fourth capacitor plate includes a second hole overlapping the third capacitor plate, and a size of the second hole is different from that of the first hole.

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

Abstract: A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.

Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.

Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.

Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Abstract: A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.

Abstract: A memory circuit includes a plurality of memory cells arranged into columns and one or more pairs of adjacent rows and one or more first word lines. Each memory cell of the plurality of memory cells includes a data node, a first access node, and a first pass gate coupled to the first access node and configured to selectively alter a voltage level at the first access node according to a voltage level at the data node if the first pass gate is turned on. A word line of the one or more first word lines is coupled with the first pass gates of a pair of the one or more pairs of adjacent rows, and the first pass gates of the pair of the one or more pairs of adjacent rows are configured to be selectively turned on responsive to a voltage level at the word line.

Abstract: In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

Abstract: A circuit comprises a first layer and a second layer separate from the first layer. The first layer comprises a power line, a first transistor coupled to the power line, a second transistor coupled to the power line, and a first line coupling the first transistor and the second transistor. The second layer comprises a ground line, a third transistor coupled to the ground line, a fourth transistor coupled to the ground line, and a second line coupling the third transistor and the fourth transistor. The circuit also comprises an inter-layer interconnect that couples the first transistor and the third transistor. The inter-layer interconnect also couples the second transistor and the fourth transistor.

Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.

Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating film which covers the source/drain region and the gate electrode of the first transistor; and a first contact plug which is formed in the insulating film and is connected to the source/drain region or the gate electrode of the first transistor, wherein the first contact plug includes a first column section which extends in a thickness direction of the insulating film and is in contact with the source/drain region or the gate electrode of the first transistor, and a first flange section which juts out from an upper portion of the first column section in a direction parallel to a surface of the insulating film, and an upper surface of the first flange section is planarized.

Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.

Abstract: Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.

Abstract: SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

Abstract: A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Abstract: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.

Abstract: Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

Abstract: An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET, and a first pull-down FinFET and a second pull-down FinFET forming cross-latched inverters with the first pull-up FinFET and the second pull-up FinFET. A first pass-gate FinFET is connected to drains of the first pull-up FinFET and the first pull-down FinFET. A second pass-gate FinFET is connected to drains of the second pull-up FinFET and the second pull-down FinFET, wherein the first and the second pass-gate FinFETs are p-type FinFETs. A p-well region is in a center region of the SRAM cell and underlying the first and the second pull-down FinFETs. A first and a second n-well region are on opposite sides of the p-well region.

Abstract: A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.

Abstract: A variable resistive memory device includes a bit line, a word line, first electrodes and second electrodes, which are respectively arrayed in different directions, wherein a unit cell including a variable resistive material layer interposed between the first electrode and the second electrode is located at every intersection between the first electrode and the second electrode.

Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.

Abstract: Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.