Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.

Abstract: An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.

Abstract: An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.

Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

Abstract: A gate driving circuit includes a plurality of stages outputting gate signals to a plurality of gate lines. Each of the stages includes a circuit transistor, a capacitor part, a first connecting electrode and a second connecting electrode. The circuit transistor outputs the gate signal to an output electrode in response to a control signal inputted to a control electrode. The capacitor part is disposed adjacent to the circuit transistor, and includes a first electrode, a second electrode disposed over the first electrode, a third electrode disposed over the second electrode and a fourth electrode disposed over the third electrode. The first connecting electrode electrically connects the control electrode to the first and third electrodes. The second connecting electrode electrically connects the output electrode to the second and fourth electrodes.

Abstract: An object of the present invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a display device of the present invention is to comprise an insulating layer having an opening, a first conductive layer formed in the opening, and a second conductive layer formed over the insulating layer and the first conductive layer, wherein the first conductive layer is wider and thicker than the second conductive layer, and the second conductive layer is formed by spraying a droplet including a conductive material.

Abstract: A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode.

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.

Abstract: An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.

Abstract: According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less.

Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: An organic light emitting diode display includes a plurality of pixels. Each pixel includes a light emitting element and a driving transistor coupled to the light emitting element. The pixels may be arranged in a matrix. The pixels include first pixels, second pixels, and third pixels, the driving transistors of the first to the third pixels occupy different areas, and the light emitting elements of the first to the third pixels occupy substantially equal area.

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire

Abstract: An organic light emitting device according to an embodiment includes a thin film transistor substrate including a plurality of thin film transistors and an over-coating film formed on the thin film transistors. The over-coating film includes a curved surface on at least two pixels among pixels of different colors and the slope angles of depressed portions forming the curved surface are respectively different from each other depending on the colors of the pixels. A plurality of first electrodes formed on the over-coating film includes a surface formed according to the curved surface, an organic light emitting member formed on the first electrodes includes a surface formed according to the curved surface, and a second electrode formed on the organic light emitting member includes a surface formed according to the curved surface. Slope angles of the depressed portions increase according to a decrease of wavelengths of the colors of the pixels.

Abstract: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly overlap with the semiconductor layer with a gate insulating film interposed therebetween In the semiconductor layer, the first region is electrically connected to the gate electrode through a first electrode to which an AC signal is input, the second region is electrically connected to a capacitor element through a second electrode, the third region overlaps with the gate electrode and contains an impurity element at lower concentrations than each of the first region and the second region.

Abstract: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10) and the color filter-side substrate (50). In this electrochromic display, the TFT (14) is formed to have an area not less than 30% of the area of the pixel, thereby supplying a larger current. Consequently, oxidation-reduction reaction in the electrochromic phenomenon proceeds at a higher rate, thereby enabling a high-speed response.

Abstract: Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of ?4 to ?3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

Abstract: The present invention relates to a thin film transistor array substrate comprising a gate line and a data line that are separated by an insulting layer and intersecting each other to define a pixel, wherein a data auxiliary line is disposed adjacent to an intersection portion between the data line and the gate line, and both ends of the data auxiliary line are on two sides of the intersection portion and connected with the data lines, respectively.

Abstract: A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

Abstract: The present invention provides a liquid crystal display device to be operated at high speed and with high precision by improving performance of a thin-film transistor without increasing cross capacity of gate lines and data lines. On an upper layer of a gate insulator GI at an intersection of gate lines GL and data lines DL to be prepared on an active matrix substrate SUB1, which makes up a liquid crystal display panel of a liquid crystal display device, an insulating material with low dielectric constant is dropped by ink jet coating method to prepare another insulator LDP in order to improve performance characteristics of the thin-film transistor to be prepared on a silicon semiconductor layer SI without increasing cross capacity on said intersection.

Abstract: An array substrate includes a gate line, a data line, a switching device, a transmissive electrode, a reflective electrode and a compensating wiring. A pixel region includes first and second regions. The switching device is connected to the gate line and the data line. The transmissive electrode is connected to the switching device. The transmissive electrode is formed in the first region. The reflective electrode is insulated from the transmissive electrode. The reflective electrode is formed in the second region that is adjacent to the first region. The compensating wiring is connected to the switching device. The compensating wiring faces the reflective electrode in the second region with an insulation layer interposed therebetween. Thus, both of a reflectivity of the reflective electrode and a transmissivity of the transmissive electrode are enhanced simultaneously, while the liquid crystal display apparatus maintains a uniform cell gap.

Abstract: A gate electrode (wiring) (40) having a Cu layer (40a) surrounded by a coating film (40b) made of titanium or titanium oxide; a TFT substrate (31) comprising the gate electrode (wiring) (40) and a LCD comprising a pair of opposing substrates and a liquid crystal disposed between the opposing substrates, wherein one of the pair of opposing substrates is a TFT substrate (31), are disclosed.

Abstract: A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern. A protection circuit is electrically connected to the gate and data lines, and disposed in an outer peripheral portion of a display region in which the switching elements and the display electrodes are formed on the one side of the substrate. A common line is insulated from the protection circuit, connected to the conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region.

Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.

Abstract: A thin film panel is provided, which includes a first signal line and a second signal line crossing the first signal line and formed on a different layer from the first signal line. The second signal line includes an expansion having an enlarged area and at least one cutout, and is disposed adjacent to a crossing region where the second signal line crosses the first signal line.

Abstract: A device includes: a first electrical contact; a second electrical contact; a semiconducting or semimetallic organic layer disposed at least partially between the first and second electrical contacts; and a tunneling barrier layer disposed at least partially between the semiconducting or semimetallic organic layer and the first electrical contact. The tunneling barrier layer has a thickness effective to enable flow of an electrical current through the tunneling barrier layer responsive to an operative electrical bias applied across the first and second electrical contacts, the electrical current exhibiting negative differential resistance for at least some applied electrical bias values. Circuits are also disclosed that utilize one or more negative differential resistance polymer diodes to implement logic, memory, or mixed signal applications.

Abstract: A liquid crystal display panel and a fabricating method thereof comprising an image sensing capability, image scanning, and touch inputting. In the liquid crystal display device, a gate line and a data line are formed to intersect each other on a substrate to define a pixel area in which a pixel electrode is positioned. A first thin film transistor is positioned at an intersection area of the gate line and the data line. A sensor thin film transistor senses light having image information and supplied with a first driving voltage from the data line. A driving voltage supply line is positioned in parallel to the gate line to supply a second driving voltage to the sensor thin film transistor.

Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.

Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Abstract: A liquid crystal display (LCD) device includes a gate line and a data line crossing each other to define a pixel region on a first substrate, a thin film transistor connected to the gate line and the data line, a first protrusion and a second protrusion formed on the first substrate, a pixel electrode connected to the thin film transistor in the pixel region, a first patterned spacer and a second patterned spacer formed on a second substrate facing the first substrate, wherein the first patterned spacer corresponds to the first protrusion, and the second patterned spacer corresponds to the second protrusion.

Abstract: A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.

Abstract: A display device having a gate wiring including a first conductive material, an insulating film over the gate wiring, a semiconductor film over the insulating film, a source electrode and a drain electrode including a second conductive material formed over a source region and a drain region, and a pixel electrode including a transparent conductive film. The device includes a first terminal portion electrically connected to the gate wiring and having a first layer including a same material as the first conductive material and a second layer including a same material as the transparent conductive film. The device further includes a second terminal portion electrically connected to the source wiring and having a first layer including a same material as the second conductive material and a second layer including a same material as the transparent conductive film. An IC chip may be electrically connected to at least one of the first and second terminal portions.

Abstract: A method for manufacturing a semiconductor device having steps of forming an amorphous semiconductor on a substrate having an insulating surface; patterning the amorphous semiconductor to form plural first island-like semiconductors; irradiating a linearly condensed laser beam on the plural first island-like semiconductors while relatively scanning the substrate, thus crystallizing the plural first island-like semiconductors; patterning the plural first island-like semiconductors that have been crystallized to form plural second island-like semiconductors; forming plural transistors using the plural second island-like semiconductors; and forming a unit circuit using a predetermined number of the transistors, where the second island-like semiconductors used for the predetermined number of the transistors are formed from the first island-like semiconductors that are different from each other.

Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on-the semiconductor layer corresponding to the channel to protect the semiconductor layer.

Abstract: An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided over an insulator having openings. The island-shaped semiconductor layer includes embedded semiconductor layers and a thin film semiconductor layer. The embedded semiconductor layers have a larger thickness than that of the thin film semiconductor layer.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

Abstract: An amorphous-silicon thin film transistor and a shift register shift having the amorphous-silicon TFT include a first conductive region, a second conductive region and a third conductive region. The first conductive region is formed on a first plane spaced apart from a substrate by a first distance. The second conductive region is formed on a second plane spaced apart from the substrate by a second distance. The second conductive region includes a body conductive region and two hand conductive regions elongated from both ends of the body conductive region to form an LI-shape. The third conductive region is formed on the second plane. The third conductive region includes an elongated portion. The elongated portion is disposed between the two hand conductive regions of the second conductive region. The amorphous-silicon TFT and the shift register having the amorphous TFT reduce a parasitic capacitance between the gate electrode and drain electrode.

Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.

Abstract: A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern. A protection circuit is electrically connected to the gate and data lines, and disposed in an outer peripheral portion of a display region in which the switching elements and the display electrodes are formed on the one side of the substrate. A common line is insulated from the protection circuit, connected to the conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region.

Abstract: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

Abstract: A semiconductor device having high reliability, in which TFTs with appropriate structures for the circuit functions are arranged, is provided. Gate insulating films (115) and (116) of a driver TFT are designed thinner than a gate insulating film (117) of a pixel TFT in a semiconductor device having a driver circuit and a pixel section on the same substrate. In addition, the gate insulating films (115) and (116) of the driver TFT and a dielectric (118) of a storage capacitor are formed at the same time, so that the dielectric (118) may be extremely thin, and a large capacity can be secured.

Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

Abstract: A liquid crystal display device includes a substrate, a gate line and a data line intersected with each other to define a pixel region on the substrate, a thin film transistor having a nanowire channel layer in an intersection region of the gate line and the data line, and a pixel electrode formed in the pixel region.