Read-only Memory, Rom, Structure (epo) Patents (Class 257/E27.102)
  • Patent number: 10446751
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
  • Patent number: 10108305
    Abstract: In particular embodiments, an apparatus includes an insulator coupled to one or more electrodes that are configured to passively sense charge displacement or a change in characteristics of electromagnetic signals in an environment.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Company, Ltd.
    Inventors: Ernest Rehmi Post, Olivier Bau, Iliya Tsekov, Sajid Sadi, Mike Digman, Vatche Attarian, Sergi Consul, Cody Wortham
  • Patent number: 10014065
    Abstract: Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: July 3, 2018
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9589640
    Abstract: A method of a operating a data storage device including a nonvolatile memory device and a memory controller is provided. The method includes reading a first selection transistors connected to a first selection line from among a plurality of selection lines with a reference voltage, determining whether a first number of selection transistors, from among the first selection transistors, which have a threshold voltage less than the reference voltage is larger than a first reference value, and if the first number is larger than the first reference value, programming the first selection transistors to have threshold voltage larger than or equal to a target voltage.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangkwon Moon, Sang-Hwa Han, Seungkyung Ro
  • Patent number: 9478307
    Abstract: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yuki Yanagisawa
  • Patent number: 9443839
    Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 13, 2016
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
  • Patent number: 8994180
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8836076
    Abstract: A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Jun Nagayama
  • Patent number: 8786096
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8766374
    Abstract: According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventor: Douglas Smith
  • Patent number: 8742586
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 8730707
    Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8704286
    Abstract: Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8698253
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8664108
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 8604521
    Abstract: An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of the optical sensor according to a predetermined layout. Preferably, the optically controlled read only memory of the present invention is capable of providing two types or more program codes and outputting different program codes carrying different function under different lighting condition.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 10, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Yi-Tyng Wu
  • Publication number: 20130256804
    Abstract: According to one exemplary implementation, an integrated circuit (IC) includes a first memory cell transistor of a read only memory (ROM) array, the first memory cell transistor including a first metal gate of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor of the ROM array, the second memory cell transistor including a second metal gate of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: BROADCOM CORPORATION
    Inventor: Wei Xia
  • Patent number: 8541775
    Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Beom Baek, Young Ho Lee, Jin Ku Lee, Mi Ri Lee
  • Patent number: 8497544
    Abstract: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 30, 2013
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Ming Li, Donald R. Mullen, Frederick Ware, Kevin S. Donnelly
  • Patent number: 8497172
    Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 30, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
  • Patent number: 8497582
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8492875
    Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 0 <x<2.5 when the tantalum oxide is represented by TaOx; and wherein when a resistance value between the electrodes is in the low-resistance state is RL, a resistance value between the electrodes is in the high-resistance state is RH, and a resistance value of a portion other than the variable resistance layer in a current path connecting a first terminal to a second terminal via the first electrode, the variable resistance layer and the second electrode, is R0, R0 satisfies RL <R0.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Osano, Satoru Fujii, Shunsaku Muraoka
  • Patent number: 8466519
    Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 18, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
  • Patent number: 8466509
    Abstract: The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tetsuya Yamada
  • Patent number: 8455923
    Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 4, 2013
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Han-Rei Ma, Fu-Chang Hsu
  • Patent number: 8390076
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Suzuki, Hiroshi Shimode, Takeshi Shimane, Norihisa Arai, Minori Kajimoto
  • Patent number: 8378407
    Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: February 19, 2013
    Assignee: Tower Semiconductor, Ltd.
    Inventors: Mikalai Audzeyeu, Yuriy Makarevich, Siarhei Shvedau, Anatoly Belous, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
  • Patent number: 8350326
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi
  • Patent number: 8283731
    Abstract: The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Kilopass Technologies, Inc.
    Inventor: Harry Shengwen Luan
  • Patent number: 8278167
    Abstract: Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8264031
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: September 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kidoh, Hiroyasu Tanaka, Tomoko Fujiwara, Megumi Ishiduki, Yosuke Komori, Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Ryouhei Kirisawa, Junya Matsunami, Hideaki Aochi
  • Publication number: 20120223395
    Abstract: The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a power line, and each cell of a second subset of ROM cells has a source electrically isolated.
    Type: Application
    Filed: May 15, 2012
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8237199
    Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sun Sel, Jung-Dal Choi, Chang-Seok Kang, Chang-Hyun Lee, Jang-Sik Lee, Vie-Na Kim
  • Patent number: 8227851
    Abstract: It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device of the invention includes an element group including a plurality of transistors over a substrate; a first conductive film functioning as an antenna over the element group; a second conductive film surrounding the first conductive film; an insulating film covering the first and second end portions; and a third conductive film over the insulating film. The first conductive film is provided in the shape of a coil, and each end portion of the first conductive film is connected to the element group. First and second end portions of the second conductive film are not connected to each other.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Koji Dairiki, Yuugo Goto
  • Patent number: 8227873
    Abstract: According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventor: Douglas Smith
  • Patent number: 8193573
    Abstract: A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 5, 2012
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Ming Li, Donald R. Mullen, Frederick Ware, Kevin S. Donnelly
  • Publication number: 20120119282
    Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
  • Publication number: 20120098052
    Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 26, 2012
    Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
  • Patent number: 8106463
    Abstract: A ROM memory cell has significantly less total area than previously known ROM memory cells. Instead of using only one layer in the manufacturing process to program the memory cells, at least two layers are used to program the memory cells. This flexibility allows the memory cell to be reduced in area, which in turn produces a ROM that is more area efficient and consequently lower in cost. As the bitline length and capacitance are reduced, the speed and power consumption are also improved.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: January 31, 2012
    Assignee: ARM, Inc.
    Inventors: Sudhir S. Moharir, Zhigeng Liu
  • Publication number: 20110316092
    Abstract: A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
    Type: Application
    Filed: March 17, 2011
    Publication date: December 29, 2011
    Inventors: Seung-Jin Yang, Yong-Tae Kim, Hyuck-Soo Yang, Jung-Ho Moon
  • Publication number: 20110298054
    Abstract: The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Inventor: Harry Shengwen Luan
  • Patent number: 8063432
    Abstract: A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Publication number: 20110248356
    Abstract: According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 13, 2011
    Inventor: Douglas Smith
  • Patent number: 8008710
    Abstract: A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Publication number: 20110188309
    Abstract: According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from the first circuit unit toward the second circuit unit. A high impurity concentration region in a first connection region of one diffusion layer of the first transistor is connected to the first interconnect, and other diffusion layer is connected to the third interconnect. A distance from the first connection region to a gate is longer than a distance from the second connection region to a gate. An midpoint region with a narrower width than the first connection region is provided between the gate and the first connection region of the one diffusion layer of the first transistor.
    Type: Application
    Filed: January 26, 2011
    Publication date: August 4, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masato ENDO
  • Patent number: 7986015
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: July 26, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Publication number: 20110170330
    Abstract: The disclosed memory cell (10) comprises a graphene layer (16) having controllable resistance states representing data values of the memory cell (10) In one exemplary embodiment a non-volatile memory is provided by having a ferroelectric layer (18) control the resistance states. In the exemplary embodiment, binary ‘0’s and ‘1’s are respectively represented by low and high resistance states of the graphene layer (16), and these states are switched in a non-volatile manner by the polarization directions of the ferroelectric layer (18).
    Type: Application
    Filed: September 23, 2009
    Publication date: July 14, 2011
    Applicant: NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Barbaros Oezyilmaz, Yi Zheng, Guang Xin Ni, Chee Tat Toh
  • Patent number: 7948023
    Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Takebuchi, Fumitaka Arai
  • Patent number: 7928516
    Abstract: A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyohito Nishihara
  • Patent number: 7923813
    Abstract: A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: April 12, 2011
    Assignee: NXP B.V.
    Inventors: Paul Van Der Sluis, Andrei Mijiritskii, Pierre H. Woerlee, Victor M. G Van Acht, Nicolaas Lambert