Ferroelectric Non-volatile Memory Structure (epo) Patents (Class 257/E27.104)
  • Patent number: 11063112
    Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 13, 2021
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 11031400
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10552258
    Abstract: A semiconductor device that is less likely to be affected by a soft error is provided. The semiconductor device includes a first memory, a second memory, a processor that can be connected to the first memory and the second memory, and a selector for selectively connecting one of the first memory and the second memory to the processor. The probability of occurrence of a soft error of the first memory is higher than that of the second memory. When an error derived from a soft error is detected in the first memory, the selector connects the second memory to the processor. The semiconductor device can stably operate even when moved from an environment where a soft error is less likely to occur to an environment where a soft error is likely to occur.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumika Akasawa, Seiichi Yoneda
  • Patent number: 10374013
    Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 6, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Abhijit Bandyopadhyay, Christopher J. Petti, Natalie Nguyen, Brian Le
  • Patent number: 10367004
    Abstract: A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: July 30, 2019
    Assignee: NUSTORAGE TECHNOLOGY CO., LTD.
    Inventors: Fu-Chou Liu, Yung-Tin Chen
  • Patent number: 9799388
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 24, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Eric S. Carman
  • Patent number: 9747969
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 29, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Eric S. Carman
  • Patent number: 9324405
    Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 26, 2016
    Assignee: Radiant Technologies, Inc.
    Inventors: Joseph T. Evans, Jr., Calvin B. Ward
  • Patent number: 9041083
    Abstract: Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov
  • Patent number: 9035458
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Patent number: 8980647
    Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8981440
    Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Patent number: 8956881
    Abstract: A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO2 film) of a predetermined pattern is formed on the Pt film, and the Pt film and the upper electrode film are etched. Then, an insulating protective film is formed on an entire surface, and a side surface of the upper electrode film is covered with the insulating protective film. Next, the ferroelectric film and the lower electrode film are etched, thus forming a ferroelectric capacitor.
    Type: Grant
    Filed: February 16, 2013
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Patent number: 8952426
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Patent number: 8952436
    Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8896040
    Abstract: A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 25, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Hyun Lee
  • Patent number: 8860103
    Abstract: A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Shuto
  • Patent number: 8822285
    Abstract: A nonvolatile memory device includes a substrate including a cell region, contact regions and dummy contact regions. The contact regions and the dummy contact regions alternately are disposed. A plurality of word lines stacked at the cell region of the substrate and contact groups stacked at the contact regions and the dummy contact regions of the substrate. The contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung Min Hwang, Il Seok Seo
  • Patent number: 8803263
    Abstract: An object of the invention is to ensure the thermal stability of magnetization even when a magnetic memory element is miniaturized. A magnetic memory element includes a first magnetic layer (22), an insulating layer (21) that is formed on the first magnetic layer (22), and a second magnetic layer (20) that is formed on the insulating layer (21). At least one of the first magnetic layer (22) and the second magnetic layer (20) is strained and deformed so as to be elongated in an easy magnetization axis direction of the magnetic layer (22) or (20) or compressive strain (101) remains in any direction in the plane of at least one of the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: August 12, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Michiya Yamada, Yasushi Ogimoto
  • Patent number: 8786040
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • Patent number: 8779537
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 15, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger Klas Malmhall, Yuchen Zhou
  • Patent number: 8772748
    Abstract: A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuaki Yasutake
  • Patent number: 8742479
    Abstract: A transistor is formed on a semiconductor substrate, and thereafter a first insulating film is formed. Subsequently, a ferroelectric capacitor is formed on the first insulating film, and then a second insulating film is formed on the ferroelectric capacitor. Thereafter, the upper surface of the second insulating film is planarized. Subsequently, a contact hole which reaches one of impurity regions of the transistor is formed, and thus a plug is formed by embedding a conductor in the contact hole. Thereafter, a hydrogen barrier layer is formed of aluminum oxide or the like. Then, a third insulating film is formed on the hydrogen barrier layer. Subsequently, contact holes which are connected to the ferroelectric capacitor and the plug are formed. Thereafter, a conductor is embedded in the contact holes, and thus interconnections are formed.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8728901
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: May 20, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas Davenport, John Cronin
  • Patent number: 8723248
    Abstract: In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Yasuda, Jun Fujiki
  • Patent number: 8724368
    Abstract: A semiconductor device includes first to fourth memory cells and each memory cell includes a first gate electrode, a ferroelectric film, a semiconductor film, a source electrode, a drain electrode, a paraelectric film and a second gate electrode. The ferroelectric film is interposed between the first gate electrode and the semiconductor film, the source electrode and the drain electrode are interposed between the semiconductor film and the paraelectric film. The first gate electrode, the ferroelectric film, the source electrode, and the drain electrode constitute a first semiconductor transistor. The second gate electrode, the paraelectric film, the source electrode, and the drain electrode constitute a second semiconductor transistor.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: May 13, 2014
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Kaneko
  • Publication number: 20140084352
    Abstract: Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode. The second electrode may be comprised of a second conductor, and the cap layer may have a composition that is free of titanium. The second electrode may be formed by etching a layer of a material formed on a layer of the second conductor to define a hardmask and then modifying the remaining portion of that material in the hardmask to have a comparatively less etch rate, when exposed to a chlorine-based reactive ion etch chemistry, than when initially formed.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James E. Beecher, William J. Murphy, James S. Nakos, Bruce W. Porth
  • Patent number: 8652855
    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Robert Summerfelt, Hasibur Rahman, John Paul Campbell
  • Patent number: 8648401
    Abstract: A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Huang Lai, Sheng-Huang Huang, Kuo-Feng Huang, Ming-Te Liu, Chun-Jung Lin, Ya-Chen Kao, Wen-Cheng Chen
  • Patent number: 8643081
    Abstract: According to one embodiment, a semiconductor memory device comprises a first layer, a first conductive layer, a insulating layer, and a second conductive layer stacked on a substrate, a block insulating layer on inner surfaces of a pair of through-holes formed in the first conductive layer, the insulating layer, and the second conductive layer, and on an inner surface of a connecting hole connecting lower ends of the pair of through-holes, a charge storage layer on the block insulating layer, a second layer on the charge storage layer, and a semiconductor layer on the second layer. The second layer includes an air gap layer on the charge storage layer in the pair of through-holes, and a third conductive layer on the charge storage layer in the connecting hole.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Fujiwara, Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 8642358
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: February 4, 2014
    Assignees: Hynix Semiconductor Inc., Grandis, Inc.
    Inventor: Min Suk Lee
  • Patent number: 8614104
    Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 24, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8614135
    Abstract: A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Eun, JaeHee Oh
  • Patent number: 8582343
    Abstract: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture and hydrogen into the underlayer is provided between the ferroelectric capacitor layer and the passivation film, and the passivation film is characterized by containing a novolac resin.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8574927
    Abstract: Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Min-Hwa Chi, Xiufeng Han, Guoqiang Yu
  • Patent number: 8575589
    Abstract: A nonvolatile semiconductor memory device includes a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nagashima, Koichi Kubo, Hirofumi Inoue
  • Patent number: 8558294
    Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8552484
    Abstract: The semiconductor device according to the present invention comprises: a ferroelectric capacitor 42 formed above a semiconductor substrate 10 and including a lower electrode 36, a ferroelectric film 38 formed on the lower electrode 36 and an upper electrode 40 formed on the ferroelectric film 38; a silicon oxide film 60 formed above the semiconductor substrate 10 and the ferroelectric capacitor 42 and having the surface planarized; a flat barrier film 62 formed on the silicon oxide film 60 with a silicon oxide film 61 formed therebetween, for preventing the diffusion of hydrogen or water; a silicon oxide film 64 formed above the barrier film 62 and having the surface planarized; and a flat barrier film 78 formed on the silicon oxide film 74 with a silicon oxide film 76 formed therebetween, for preventing the diffusion of hydrogen or water.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8541247
    Abstract: An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 24, 2013
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Antoine Khoueir, Brian Lee, Patrick J. Ryan
  • Patent number: 8536067
    Abstract: A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer containing an organic compound, a temperature is limited because the layer containing the organic compound can be influenced depending on a temperature for forming the electrode. A forming method for the electrode is limited due to this limitation of a temperature. Therefore, there are problems that an expected electrode cannot be formed, and miniaturization of an element is inhibited. A semiconductor device includes a memory element and a switching element which are provided over a substrate having an insulating surface. The memory element includes first and second electrodes, and a layer containing an organic compound, which are provided on the same plane. A current flows from the first electrode to the second electrode. The first electrode is electrically connected to the switching element.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takehisa Sato
  • Patent number: 8518791
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8519376
    Abstract: Nonvolatile resistive memory devices are disclosed. In some embodiments, the memory devices comprise multilayer structures including electrodes, one or more resistive storage layers, and separation layers. The separation layers insulate the resistive storage layers to prevent charge leakage from the storage layers and allow for the use of thin resistive storage layers. In some embodiments, the nonvolatile resistive memory device includes a metallic multilayer comprising two metallic layers about an interlayer. A dopant at an interface of the interlayer and metallic layers can provide a switchable electric field within the multilayer.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: August 27, 2013
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Velikov Dimitrov, Insik Jin, Haiwen Xi
  • Patent number: 8518792
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8497544
    Abstract: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 30, 2013
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Ming Li, Donald R. Mullen, Frederick Ware, Kevin S. Donnelly
  • Patent number: 8492875
    Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 0 <x<2.5 when the tantalum oxide is represented by TaOx; and wherein when a resistance value between the electrodes is in the low-resistance state is RL, a resistance value between the electrodes is in the high-resistance state is RH, and a resistance value of a portion other than the variable resistance layer in a current path connecting a first terminal to a second terminal via the first electrode, the variable resistance layer and the second electrode, is R0, R0 satisfies RL <R0.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Osano, Satoru Fujii, Shunsaku Muraoka
  • Patent number: 8482044
    Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hamamoto
  • Patent number: 8482970
    Abstract: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: July 9, 2013
    Assignee: Seagate Technology LLC
    Inventor: Dimitar V. Dimitrov
  • Patent number: 8455266
    Abstract: A memory device and method for manufacturing the memory device are provided. The memory device including a first electrode, a first ferroelectric polymer layer over the first electrode, a second electrode over the first ferroelectric polymer layer, a second ferroelectric polymer layer over the second electrode, a third electrode over the second ferroelectric polymer layer, and a protective layer between the first and second ferroelectric polymer layers. The first, second and third electrodes and the first and second ferroelectric polymer layers define first and second ferroelectric capacitor structures, the second electrode being common to the first and second ferroelectric capacitor structures.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: June 4, 2013
    Assignee: Sony Corporation
    Inventors: Sunil Madhukar Bhangale, Takehisa Ishida
  • Patent number: 8455935
    Abstract: A ferroelectric film comprising polyaminodifluoroborane (PADFB). Also a memory device utilizing the ferroelectric film, a method of fabricating a ferroelectric polymer and a ferroelectric solution.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 4, 2013
    Assignees: Sony Corporation, Agency for Science, Technology, and Research
    Inventors: Takehisa Ishida, Sunil Madhukar Bhangale, Han Hong, Christina Li Lin Chai