Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

Abstract: Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility.

Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

Abstract: An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an upper electrode being in contact with the first trench-type insulating region and formed on the lower electrode with the first insulating film interposed therebetween; and a gate electrode being in contact with the second trench-type insulating region and formed on a channel region with the second insulating film interposed therebetween, in which a shape of at least a part of an end of the lower electrode forming region in contact with the first insulating film is sharper than a shape of an end of the channel region in contact with the second insulating film.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.

Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

Abstract: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A further method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.

Abstract: An exemplary read only memory cell (200) includes a semiconductor layer (220), a gate stack (230), and a gate electrode (240). The gate stack includes a tunnel film (231), a charge storing layer (232), and a block layer (233) sequentially stacked adjacent to the semiconductor layer. The gate electrode is adjacent to the block layer. The charge storing layer is configured to store charges when data is written to the read only memory cell. The charge storing layer comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is provided where the at least two sub-layers adjoin each other. A method for manufacturing the read only memory cell is also provided.

Abstract: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.

Abstract: Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed between a source region and a drain region at each of the on-cell and the off-cell. The on-cell may include a cell diffusion region between the select gate pattern and the memory gate pattern.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.

Abstract: The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of the substrate transistors.

Abstract: A one-time programmable memory. The memory has a substrate, a diffused electrode disposed on the substrate, a shallow trench isolation (STI) region formed on the substrate, a insulator formed on the STI region and the substrate, and a second electrode. The insulator separates the second electrode from the diffused electrode. At least a part of the second electrode overlaps at least a part of the STI region.

Abstract: A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage, the third and fourth active zones being mutually connected via an electrically conducting connection external to the substrate. The value of the binary data item is defined by an implantation of a chosen type in a predetermined part of the substrate region or in the third and fourth active zones.

Abstract: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of gate electrodes each including an electric charge storage layer formed on the semiconductor substrate through a first insulator, first and second conductor layers, and a second insulator disposed between the electric charge storage layer and the first conductor layer, a barrier insulator provided between the gate electrodes and being in contact with side surfaces alone of the gate electrodes, and an interlayer insulator provided in contact with an upper surface of the second conductor layer.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on the gate insulating film. The nonvolatile semiconductor memory device also includes electric charge storage insulating films formed on side surfaces of the control gate, memory gates formed on side surfaces of the sidewall insulating films to be higher than the sidewall insulating film, and a silicide film formed to connect the memory gates and the control electrode.

Abstract: A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer are sequentially formed over the substrate. A floating gate is defined in the memory cell region and the top layer and the first conductive layer of the high voltage circuit region are removed. The exposed silicon oxide layer is thickened. Thereafter, the top layer is removed and then a barrier layer is formed on the exposed surface of the floating gate. A second conductor layer is formed over the substrate, and then a gate is defined in the high voltage circuit region and a control gate is defined in the memory cell region.

Abstract: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.

Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.

Abstract: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.

Abstract: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of gate electrodes each including an electric charge storage layer formed on the semiconductor substrate through a first insulator, first and second conductor layers, and a second insulator disposed between the electric charge storage layer and the first conductor layer, a barrier insulator provided between the gate electrodes and being in contact with side surfaces alone of the gate electrodes, and an interlayer insulator provided in contact with an upper surface of the second conductor layer.

Abstract: A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a second element isolating region and includes a second gate insulating film and a second gate electrode. The upper part of the first and second element isolating regions project from a semiconductor substrate and their corners are curved. The width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region is equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.

Abstract: To address problems encountered during the fabrication of a nonvolatile memory cell, such as preventing top oxide loss, preventing contact between the nitride and the polysilicon, and reducing the problem of BD over-diffusion, various fabrication embodiments are used. In one approach, the top dielectric of an ONO structure is formed at the same time as the oxide covering the implanted regions. In another approach, another dielectric structure is formed on the implanted regions and on the top oxide of the charge storage structure. In yet another approach, a cleaning process following ion implantation is performed prior to forming the top oxide of the ONO structure. These approaches also apply to floating gate nonvolatile memories.

Abstract: A control gate includes a first conductive film formed in contact with an inter-gate insulating film and a second conductive film electrically connected to the first conductive film. An inter-level insulating film which insulates first and second stacked gate structures from each other. The inter-level insulating film includes a first insulating film, a second insulating film, and a third insulating film formed between the first and second insulating films. The first insulating film insulates the floating gates from each other and portions of the control gates from each other. The second and third insulating films insulate the other portions of the control gates from each other. The third insulating film has a selective etching ratio with respect to the first and second insulating films.

Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Abstract: The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside trenches of a semiconductor substrate, said U-shaped MOSFETS comprising a multilayer dielectric, especially an ONO dielectric, for trapping charges; source/drain areas are provided between the U-shaped MOSFETS in intermediate spaces located between the rows that extend parallel to the gaps; insulating trenches are provided in the source/drain areas between the U-shaped MOSFETS of adjacent gaps, down to a certain depth in the semiconductor substrate, said insulating trenches cutting up the source/drain areas into respective bit lines; the insulating trenches are filled with an insulating material; and word lines are provided for connecting respective rows of U-shaped MOSFETS.