Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging, and a method of fabricating the same. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.

Abstract: A flat panel display and method for fabricating the same are disclosed. The flat panel display includes a substrate. Signal lines are arranged on the substrate in a matrix shape, and a unit pixel region defined by crossing arrangement of the signal lines, has a pixel driving circuit region and an emission region. A pixel driving TFT positioned in the pixel driving circuit region, includes a semiconductor layer and a gate electrode corresponding to a predetermined portion of the semiconductor layer. The gate electrode is formed on a same layer as the signal lines. A pixel electrode, electrically connected to the pixel driving TFT, is positioned in the emission region.

Abstract: A sensor and method for widening a dynamic range of sensor circuitry for sensing energy, such as light energy. The sensor circuitry includes a sensor and recharge circuitry for sharing additional charge with the sensor as needed during an integration period. Readout circuitry is provided to read out, after the integration period, the sense voltage remaining across the sensor and recharge information indicating whether the recharge circuitry shared charge with the sensor during the integration period. The sense voltage and recharge information read out of the sensor circuitry is used in a function to determine the total amount of energy sensed by the sensor during the integration period.

Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.

Abstract: A method of fabricating semiconductor devices. Upon formation of a trench for isolation in a cell region, a hard mask film is used as an etch mask. It is thus possible to prevent attacks of a lower layer due to deformation or loss of the etch mask.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: Provided are image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by use of silicon-germanium bipolar junction transistor complementary metal oxide semiconductor (SiGe BiCMOS) technology. In the image sensor, a PD employs a floating-base-type SiGe HBT unlike a pn-junction-based CMOS image sensor (CIS). A floating base of the SiGe HBT produces a positive (+) voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. In particular, since the SiGe HBT obtains a current gain ten times as high as that of a typical bipolar device even during the reverse operation, the SiGe HBT cannot only sense an optical (image) current signal but also amplify the optical current signal. Thus, the image sensor requires only three transistors in a pixel so that the degree of integration can increase.

Abstract: A semiconductor device including a first element including a photodiode and an amplifier circuit which amplifies output current of the photodiode, over a first insulating film; and a second element including a color filter and an overcoat layer over the color filter over a second insulating film is manufactured. The first element and the second element are attached to each other by bonding the first insulating film and the second insulating film with a bonding material. Further, the amplifier circuit is a current mirror circuit including a thin film transistor. Still further, a color film may be used instead of a color filter.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: An electro-optical device includes first switching elements which are correspondingly provided at intersections of a plurality of scanning lines and a plurality of data lines in a display region, at least three metal layers which are provided in the display region, a wiring line portion which is provided in an adjacent region of the display region and supplies signals to second switching elements through signal lines formed of at least two metal layers of the three metal layers, and an electromagnetic shield which is provided in the adjacent region of the display region. The electromagnetic shield has a first shield portion which covers the wiring line portion using metal layers other than the metal layers forming the signal lines, and a second shield portion which is electrically connected to the first shield portion and is disposed between the signal lines.

Abstract: The present invention aims to provide a solid-state imaging apparatus that realizes less leakage current, high image quality and low noise during the driving operation, and manufacturing method for the same. A MOS type imaging apparatus 1 includes an imaging region 10 and a driving region 20 both formed on a p-type silicon substrate (hereinafter called an “Si substrate”) 31. The imaging region 10 includes six pixels 11 to 16 disposed in a shape of a matrix having 2 rows and 3 columns. The driving region 20 includes a timing generation circuit 21, a vertical shift resistor 22, a horizontal shift resistor 23, a pixel selection circuit 24, and so on. All transistors included in the pixels 11 to 16 in the imaging region and the circuits 21 to 24 in the driving circuit region 20 are of n-channel MOS type.

Abstract: An object is to provide a solid state image pickup device and a camera which do not worsen a sensor performance in terms of an optical property, a saturated charge amount and the like. A solid state image sensor including a pixel region having a plurality of pixels includes at least a photodiode and an amplifying portion amplifying photocharges outputted from the photodiode in the pixel region, and further includes a well electrode for taking well potential of a well region in which the amplifying portion is arranged. Between the well electrode and the photodiode, no element isolation regions by an insulation film are arranged. Moreover, on the surface of a first semiconductor region in which the photodiode stores the charges, a second semiconductor layer of a conductivity type reverse to that of the first semiconductor region is arranged.

Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi

Abstract: A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.

Abstract: An array substrate for a liquid crystal display device includes: a data line on a substrate; a source electrode contacting the data line, a drain electrode spaced apart from the source electrode and a pixel electrode connected to the drain electrode, wherein the source electrode, the drain electrode and the pixel electrode each including a transparent conductive material; an organic semiconductor layer contacting the source and drain electrodes; a gate insulating layer on the organic semiconductor layer; a gate electrode on the gate insulating layer; a first passivation layer on the gate electrode, the first passivation layer having a gate contact hole exposing the gate electrode; and a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole.

Abstract: An overlay key for a semiconductor device is provided. The semiconductor device can include a first insulating layer having a trench serving as an outer key; and a metal layer formed on the first insulating layer including in the trench of the outer key. Here, an inner key region of the metal layer is etched. The metal layer formed in the trench of the outer key can be formed on a residual first metal remaining, for example, from a via plug formation process to inhibit contact between the remaining first metal in the trench of the outer key and a second insulating layer formed on the metal layer.

Abstract: An optical head includes a plurality of unit regions repeatedly arrayed in one direction. Each region is constituted by a light-emitting element which is driven by a current to emit light, a control transistor which is connected in parallel with the light-emitting element, and which receives gray-scale data that specifies a high gray-scale level for the light-emitting element so as to be turned off and which receives gray-scale data that specifies a low gray-scale level for the light-emitting element so as to be turned on, and a driving transistor which is connected in series with the light-emitting element to generate a current. In each of the plurality of unit regions, a thermal resistance between the light-emitting element formed in the unit region and the control transistor formed in the unit region is smaller than a thermal resistance between the light-emitting element and a control transistor formed in a unit region adjacent to the unit region.

Abstract: A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an adequate offset between the pinned surface layer and an electrically active area of a transfer gate of the pixel sensor cell. The pinned surface layer is formed by employing the same mask level as the one employed for the formation of the photodiode region, and then implanting dopants at angles other than zero degrees.

Abstract: In a solid-state image-sensing device, when image sensing is performed, in each pixel, MOS transistors T1 and T5 are turned on and a MOS transistor T6 is turned off so that a MOS transistor T2 operates in a subthreshold region. When resetting is preformed, in each pixel, the MOS transistors T1 and T5 are turned off and the MOS transistor T6 is turned on so that the gate voltage of the MOS transistor T2 is kept constant. In this state, the MOS transistor T2 is brought first into a conducting state and then, by turning a signal ?VPS to a high level, into a cut-off state. This permits a signal proportional to the threshold value of the MOS transistor T2 to be output as compensation data.

Abstract: The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film before the film is etched with a corrosive etchant. Minimizing the corrosion of the aluminum-based film may increase the yield and performance of the highly reflective pixel arrays that are formed from the aluminum-based metal for use in liquid crystal on silicon (LCOS) microprocessors for digital televisions.

Abstract: The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the reflecting material defined by gaps in a sacrificial layer. In accordance with an alternative embodiment, the reflecting surface is separated from the underlying hinge by a gap formed in an intervening layer, such as oxide. In either embodiment, walls separating adjacent pixel regions may be recessed beneath the reflecting surface to further reduce unwanted scattering of incident light and thereby enhance contrast.

Abstract: Provided is a novel structure of an active matrix TFT backplane. In order to form an auxiliary capacitor by a pixel electrode or a drain electrode of a TFT connected therewith, a base metal layer is formed on a glass substrate and a substrate insulating layer is formed on an entire surface thereof. By the structure, position alignment of the drain electrode with a counter electrode is unnecessary. An area for electrical capacitor formation is determined by size precision of the drain electrode, so a variation in electrical capacitance is suppressed to a small value.

Abstract: A thin film transistor array panel including a substrate, a plurality of data lines disposed on the substrate, an interlayer insulating layer disposed on the data lines and including contact holes through which the data lines are exposed, a plurality of source electrodes, each of the source electrodes disposed on the interlayer insulating layer and connected to the data line through the contact hole, a plurality of pixel electrodes, each of the pixel electrodes disposed on the interlayer insulating layer and including a drain electrode that faces a source electrode, organic semiconductors disposed on and partially overlapping the source electrodes and the drain electrodes, a gate insulating layer disposed on the organic semiconductors and gate lines disposed on the gate insulating layer and including gate electrodes overlapping the organic semiconductors.

Abstract: To provide an amplification type solid state image pickup device enabling lower noise, higher gain, and higher sensitivity than any conventional amplification type solid state image pickup device.

Abstract: A thin film transistor includes a semiconductor layer a source electrodes a drain electrode and a gate electrode. The semiconductor layer includes a plurality of grain boundaries disposed along a first direction. An acute angle between a gate electrode and a grain boundary prevents grain to boundaries from being formed at the boundary between a channel part and an ion doped part.

Abstract: The invention provides a downsized structure of a light emitting device, and a light emitting device which has enough reliability as a downsized light emitting device. The light emitting device comprising light emitting elements according to the invention includes a signal processing circuit disposed beside an FPC and the like that tended to be the dead space conventionally. Also, the light emitting device has a sealed structure using a barrier film in which moisture and oxygen can be blocked from outside not to come into TFTs, wirings, and the light emitting elements formed over a substrate.

Abstract: A display device includes a first display panel, a first gate driver, a second display panel and a second gate driver. The first display panel includes a first display region, in which first gate lines are formed, and a first peripheral region surrounding the first display region. The first gate driver is formed at the first peripheral region and outputs a first gate signal to the first gate lines in response to a first clock signal and a second clock signal. The second display panel is electrically connected with the first display panel. The second display panel includes a second display region, in which second gate lines are formed, and a second peripheral region surrounding the second display region. The second gate driver is formed at the second peripheral region and outputs a second gate signal to the second gate lines in response to the first clock signal and second clock signal.

Abstract: It is an object of the present invention to provide a light emitting element which can be driven at a low voltage. Other objects of the present invention are to provide a light emitting element with a high luminescent efficiency; a light emitting element with a high luminance; a light emitting element having long-life luminescence; a light emitting element and an electronic device having reduced power consumption; and a light emitting element and an electronic device which can be manufactured at low cost. The light emitting element has a light emitting layer and a barrier layer between a first electrode and a second electrode, the light emitting layer contains a base material and an impurity element, and the barrier layer is provided so as to be in contact with the first electrode. Light emission is obtained when a voltage is applied such that a potential of the second electrode becomes higher than a potential of the first electrode.

Abstract: A display apparatus includes; a substrate, a transistor formed on the substrate, a pixel electrode connected to the transistor, a wall surrounding the pixel electrode, the wall including a main wall and a sub wall, the main wall having a first height and the sub wall having a second height less than the first height of the main wall, an organic layer formed on the pixel electrode, a common electrode formed on the organic layer, and an encapsulation substrate coupled to the substrate.

Abstract: The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.

Abstract: A display device includes a first display panel including a common electrode disposed thereon, and a second display panel including; thin film transistors (“TFTs”) each including a gate electrode, a source electrode, and a drain electrode, a first passivation layer disposed on the source and drain electrodes, a second passivation layer disposed on the first passivation layer and including at least one sensing protrusion, pixel electrodes disposed on the second passivation layer and connected with the drain electrode, and at least one conductive member disposed on the sensing protrusion.

Abstract: Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other.

Abstract: A thin film transistor array panel is provided, which includes: a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas; a plurality of drain electrodes separated from the data lines; a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes; a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced ap

Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

Abstract: An array substrate for a liquid crystal display device includes a substrate including a first driving region, a second driving region, and a pixel region, the pixel region including a switching region and a storage region; a first n-type transistor in the first driving region, a second p-type transistor in the second driving region; a third transistor in the switching region, the third transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; an extension portion in the storage region and extending from the active layer; a metal pattern on the extension portion; a storage line over the metal pattern; and a pixel electrode in the pixel region and contacting the third transistor, wherein the metal pattern, the storage line and the pixel electrode form first, second and third electrodes of a storage capacitor that includes a first capacitor and a second capacitor parallel to each other.

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 ?m. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

Abstract: An LCD includes a thin film display device having a plastic insulating substrate in which lifting of the edge of the thin film is avoided which includes a display region and a non-display region; a gate line assembly formed on the plastic insulating substrate with the use of a shadow mask disposed over the plastic insulating substrate; a gate insulating layer formed on the gate line assembly in the display region; a data line formed on the gate insulating layer and a data pad formed in the non-display region and spaced away from the gate insulating layer; and a passivation layer formed on the data line.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form data lines and drain electrodes. A photoresist is formed, and the upper film is patterned using the photoresist as an etch mask to expose contact portions of the lower film of the drain electrodes. Exposed portions of the extrinsic a-Si layer and the intrinsic a-Si layer are removed, and then the photoresist and underlying portions of the extrinsic a-Si layer are removed. A passivation layer is formed and patterned along with the gate insulating layer to form contact holes exposing the contact portions of the lower film, and pixel electrodes are formed to contact the contact portions.

Abstract: The invention provides a light emitting device using transistors manufactured by the conventional process while reducing an area occupied by capacitors, whereby variations in luminance of light emitting elements caused by variations in gate voltage Vgs of the transistors are suppressed, and a luminance decay of the light emitting elements due to the degradation of light emitting materials and variations in luminance can also be suppressed.

Abstract: A liquid crystal display device and a fabricating method thereof for securing aperture ratio are disclosed. In the liquid crystal display device, a gate line is formed. A data line crosses the gate line. A thin film transistor is provided at an intersection of the gate line and the data line. A semiconductor pattern is overlapped with the data line under the data line, and includes an active layer of the thin film transistor. A step coverage does not exist between an etched edge surface of the semiconductor pattern disposed at a lower portion of the data line and an etched edge surface of the data line.

Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi

Abstract: The invention is to suppress a leak current in a photodiode and an unevenness in the leak currents. In a photoelectric converting device including a channel stop area of a higher concentration than in an element isolating insulation film formed between a photodiode, having an n-type semiconductor area formed in a p-type semiconductor, and an adjacent element, and in a p-type semiconductor layer formed under the element isolating insulation film, and a wiring layer formed in a part on the element isolating insulation film, the wiring layers on the element isolating insulation film adjacent to the photodiodes are unified in an effective area and a potential, and a p-type dark current reducing area of a higher concentration than in the channel stop area is provided in at least a part of an area opposed to the wiring layer across the element isolating insulation film.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: A pixel structure controlled by a scan line and a data line on a substrate is provided. The pixel structure comprises a thin film transistor, a resistance wire, a first pixel electrode, and a second pixel electrode, which are disposed on the substrate. Additionally, the thin film transistor is electrically connected to the scan line, the data line, and the resistance wire. Further, the first pixel electrode is electrically connected to the thin film transistor and the second pixel electrode is electrically connected to the thin film transistor by the resistance wire. Especially, a method of manufacturing a pixel structure is also provided.

Abstract: A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less than approximately 85 degrees from the plane of the top surface of the substrate.

Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.

Abstract: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Abstract: A microcrystalline germanium image sensor array. The array includes a number of pixel circuits fabricated in or on a substrate. Each pixel circuit comprises a charge collecting electrode for collecting electrical charges and a readout means for reading out the charges collected by the charge collecting electrode. A photodiode layer of charge generating material located above the pixel circuits convert electromagnetic radiation into electrical charges. This photodiode layer includes microcrystalline germanium and defines at least an n-layer, and i-layer and a p-layer. The sensor array also includes and a surface electrode in the form of a grid or thin transparent layer located above the layer of charge generating material. The sensor is especially useful for imaging in visible and near infrared spectral regions of the electromagnetic spectrum and provides imaging with starlight illumination.