Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal.

Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.

Abstract: The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N+ source/drain implant and P-channel regions are then opened for P+ source/drain implant. Prior to the N+ source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P+ source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.

Abstract: The present invention relates to an image sensor with a microlens and a method for fabricating the same with use of a bump formation process. A method for fabricating an image sensor includes the steps of: forming a passivation layer on a substrate structure provided with a photodiode and other various device elements; forming a microlens on a portion of the passivation layer; forming a microlens passivation layer for protecting the microlens from a subsequent bump formation process on the microlens; forming a pad open region by selectively etching the microlens passivation layer and the passivation layer; and forming a bump in the pad open region.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: The present invention provides an image display device which can enhance the overlapping positional accuracy of both substrates and can exhibit a prolonged lifetime and a high quality display by suppressing the generation of sparks. A plurality of island-like electrodes are arranged on a back substrate, the island-like electrodes are held at a given potential, counter electrodes which correspond to the island-like electrodes are formed on a face substrate, and the counter electrodes are connected to an anode electrode.

Abstract: A thin film transistor array panel is provided, comprising: a gate line on an insulating substrate; a storage electrode line on the insulating substrate; a gate insulating layer over the gate line and the storage electrode line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode on the semiconductor layer and separated from each other; a lower passivation layer formed on the semiconductor layer and having a first contact hole exposing the drain electrode; a color filter on the lower passivation layer; an upper passivation layer on the color filter and having a second contact hole exposing the drain electrode; and a pixel electrode connected to the drain electrode through the first and second contact holes; wherein the storage electrode line has a light blocking member parallel to the data line.

Abstract: The present invention provides a display device including a scanning line (3) formed on an insulating substrate, an auxiliary capacitance line (4), a signal line (8), a gate electrode (2) connected to the scanning line, a source electrode (7) connected to the signal line, a switching element (1) formed of the source electrode and a drain electrode (9) formed opposing the source electrode, a reflective electrode (10) and a transmissive electrode (13) that are connected to the switching element, wherein an independent strip conductor formed of a conductive film in the same layer as that for the scanning line and the auxiliary capacitance line is formed in the vicinity of the signal line within the reflective region including the reflective electrode, the independent strip conductor being connected to the drain electrode.

Abstract: A TFT array panel including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability.

Abstract: A method of manufacturing a display device is presented. The method includes mounting the memory on the printed circuit board (PCB) and writing the characteristic data in the memory. The characteristic data, which is data that is specific to a display device having a particular specification, allows an operator to verify that the correct characteristic data is being used for the display device type, size, etc. By mounting the memory on the PCB before the characteristic data is written in the memory but after the characteristic data is written in the PCB test procedure, the method allows the display device to be manufactured with fewer number of workers and fewer steps in the manufacturing process. A display device made using this method is also presented.

Abstract: A compensating light source capable of compensating for the light intensity attenuation caused by the optical path and the designing method. First, a number of the predetermined light sources, which have uniform luminance, are chosen to respectively illuminate a chart with a uniform gray scale and produce a number of scanning light beams with respect to these predetermined light sources. After that, the scanning light beams are collected and focused to form an image on the optical sensing devices with respect to a number of image pixels. These image pixels can produce a number of sensing voltages with respect to the predetermined light sources. The tube dimensions of these predetermined light sources are relative to the sensing voltages of the predetermined light sources to form relative data. The relative data and the sensing voltages with respect to the selected predetermined light source are used to design a compensating light source. Then, a check action is performed.