Abstract: An integrated circuit (IC) package includes a chip. The chip has a front-side surface and a backside surface, opposite the front-side surface. The front-side surface of the chip includes a plurality of bump sites. The integrated circuit package also includes a plurality of dies. Each of the plurality of dies are composed of integrated passive devices. The plurality of dies have conformal die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.

Abstract: A technology is proposed in which the improvement of the capability of a semiconductor device can be realized by satisfying both reduction of leakage currents and suppression of the degradation of the conductive characteristic of the semiconductor device. An electric field relaxation region ERR is formed in an outer edge region on the outside of a mesa structure MS. In addition, an electric charge implantation region EIR formed on a drift layer EPI, a resistance reduction region RR formed on the electric charge implantation region EIR, and a leakage reduction region LR formed at a sidewall portion of the mesa structure MS are formed in the mesa structure MS. In this case, the impurity concentration of the leakage reduction region LR is set larger than the impurity concentration of the electric field relaxation region ERR, and is set smaller than the impurity concentration of the resistance reduction region RR.

Abstract: A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body including a diode-structure with a pn-junction, and an edge-termination structure arranged in a peripheral area of the semiconductor body. The edge-termination structure includes an insulating region partially arranged in the semiconductor body adjacent the pn-junction and a semi-insulating region arranged on the insulating region and spaced apart from the semiconductor body. The semi-insulating region forms a resistor connected in parallel with the diode-structure.

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Abstract: A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.

Abstract: An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.

Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.

Abstract: A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body with a first semiconductor region and a second semiconductor region spaced apart from each other. A first metallization is in contact with the first semiconductor region. A second metallization is in contact with the second semiconductor region. An insulating region extends between the first semiconductor region and the second semiconductor region. A semi-insulating region having a resistivity of about 103 Ohm cm to about 1014 Ohm cm is arranged on the insulating region and forms a resistor between the first metallization and the second metallization.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract: A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

Abstract: A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.

Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.

Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Abstract: A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.

Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.

Abstract: A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

Abstract: According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region.

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Abstract: Systems and methods are disclosed for disposing high and low-resistivity portions of semiconductor substrate in proximity to an active radio frequency (RF) device, thereby at least partially controlling harmonic interference associated with the device. The device may be disposed above the high-resistivity portion, and at least partially surrounded by the low-resistivity portion. The high and low-resistivity portions may provide various benefits associated with interference attenuation, thermal properties, or other benefits. The low-resistivity region can be disposed an optimized distance away from the device.

Abstract: Devices and methods are provided, wherein a diode string is provided in a well and the well is biased with an intermediate voltage between voltages applied to terminals of the diode string.

Abstract: A semiconductor device comprises a piece of semiconductor material. On a surface of said piece of semiconductor material, a number of electrodes exist and are configured to assume different electric potentials. A guard structure comprises a two-dimensional array of conductive patches, at least some of which are left to assume an electric potential under the influence of electric potentials existing at said electrodes.

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A superjunction structure in the semiconductor body includes drift regions of a first conductivity type and compensation structures alternately disposed in a first direction parallel to the first surface. Each of the charge compensation structures includes a first semiconductor region of a second conductivity type complementary to the first conductivity type and a first trench including a second semiconductor region of the second conductivity type adjoining the first semiconductor region. The first semiconductor region and the first trench are disposed one after another in a second direction perpendicular to the first surface.

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract: A semiconductor device including a driving region and a dummy region disposed at both side of the driving region includes a semiconductor substrate having a plurality of active regions spaced from each by equal distances in the driving region, a dummy active region in the dummy region, and a guard ring region surrounding the active regions and the dummy active regions. The distance between the dummy active region and the active region nearest to the dummy active region is substantially the same as each distance between adjacent ones of the active regions, and is smaller than the distance between the dummy active region and a portion of the guard ring region nearest to the dummy active region.

Abstract: A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction.

Abstract: A switching transistor includes a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, having a first conductivity type and having a barrier region dopant concentration that is higher than the substrate dopant concentration. A source region is embedded in the barrier region, and has a second conductivity type and has a dopant concentration that is higher than the barrier region dopant concentration. A drain region is embedded in the barrier region and is offset from the source region. The draining region has the second conductivity type and a dopant concentration that is higher than the barrier region dopant concentration. A channel region extends between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region. An insulation region covers the channel region and is disposed between the channel region and a gate electrode.

Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.

Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.

Abstract: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.

Abstract: An electrostatic discharge protection circuit is used in an integrated circuit with a first sub-circuit working with a first working voltage source and a second sub-circuit working with a second working voltage source lower than the first working voltage source. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor transistor of a first conductive type, having a drain thereof electrically connected to a pad of the integrated circuit, and gate, source and bulk thereof electrically connected to a bulk voltage; and a guard ring of the first conductive type, surrounding the first metal-oxide-semiconductor transistor of the first conductive type and coupled to the second working voltage source.

Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Abstract: A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.