Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: A semiconductor device has a high voltage circuit section disposed on a semiconductor substrate having a first conductivity. The high voltage circuit section has a well region with a second conductivity, a first heavily doped impurity region with the first conductivity and disposed on the well region, a second heavily doped impurity region having a second conductivity and disposed on the semiconductor substrate, a trench isolation region disposed between the first and second heavily doped impurity regions, and an interconnect disposed over the trench isolation region. First and second electrodes are disposed above the trench isolation region, below the interconnect, and on opposite sides of a junction between the well region and the semiconductor substrate. The first electrode is disposed above the semiconductor substrate, and the second electrode is disposed above the well region.

Abstract: A semiconductor device includes an active region with a vertical drift path of a first conduction type and with a near-surface lateral well of a second, complementary conduction type. In addition, the semiconductor device has an edge region surrounding the active region. This edge region has a variable lateral doping material zone of the second conduction type, which adjoins the well. A transition region in which the concentration of doping material gradually decreases from the concentration of the well to the concentration at the start of the variable lateral doping material zone is located between the lateral well and the variable lateral doping material zone.

Abstract: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the surface region of the semiconductor material region. The doping of the near-surface compensation doping area of the semiconductor device at least partially compensates for the doping in the transition doping area.

Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.

Abstract: A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically specifically within a channel region pedestal within the metal oxide semiconductor field effect transistor structure. The halo region aperture is filled with a halo region formed using an epitaxial method, thus the halo region may be formed physically separated from the gate dielectric. As a result, performance of the metal oxide semiconductor field effect transistor is enhanced.

Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Abstract: A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths.

Abstract: Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a conductive film is formed on the insulating film between adjacent electrodes among a first surface electrode, second surface electrodes, and a third surface electrode.

Abstract: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.

Abstract: A Semiconductor component that contains AlxGayIn1-x-yAszSb1-z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a passivation layer containing AlnGa1-nAsmSb1-m is applied at least partially on at least one lateral surface of the structuring, and the parameter n is selected in the range of 0.4 to 1 and the parameter m in the range of 0 to 1.

Abstract: A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract: An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.

Abstract: A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of the first conductivity type extending from the top surface into the body area, an isolation area surrounding the first area, a ring area of the first conductivity type surrounding the isolation area, and a coupling structure for connecting the ring area with the substrate.

Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.

Abstract: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 ?m or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 ?m or narrower.

Abstract: A semiconductor device comprises a semiconductor substrate having a first semiconductor region of a first semiconductor type, a second semiconductor region of a second conductivity type extended in the first semiconductor region, and a mesa area forming a slope along an outer circumference of the semiconductor substrate; a first electrode provided on a first principal surface of the semiconductor substrate; and a second electrode provided on a second principal surface of the semiconductor substrate that is opposed to the first principal surface; wherein the second semiconductor region comprises a main region provided in the semiconductor substrate while being brought into contact with the first electrode, the main region including an annular portion and diffused portions arranged in a spread manner in an area surrounded by the annular portion; and wherein a portion of the first semiconductor region is interposed between the diffused portions and between the diffused portions and the annular portion; and the d

Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.

Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.

Abstract: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO?VBE1+VBE2+VTH. Other embodiments are described and claimed.

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

Abstract: A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacent the first gate dielectric, wherein the first LDD region comprises arsenic; and a first deep source/drain region in the semiconductor substrate and adjacent the first gate dielectric. The first deep source/drain region comprises phosphorous, and a first phosphorous junction depth in the first deep source/drain region is greater than about three times a first arsenic junction depth in the first deep source/drain region.

Abstract: A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L1, that of the other edge on a down stream side is L2, and a relation L1>L2 is satisfied.

Abstract: A semiconductor device including a substrate of a first semiconductor type with a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: A system and method are disclosed for providing an integrated circuit low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection. In an advantageous embodiment of the present invention, a transfer gate of the input/output structure comprises at least one thick gate native (or depletion) n-channel metal oxide semiconductor (NMOS) transistor that is connected to an output pad node of the input/output structure. The thick gate native (or depletion) NMOS transistor prevents current from the output pad node from entering the input/output structure when a voltage level of the output pad node is high.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.

Abstract: An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

Abstract: A semiconductor layer of n? type is formed on a semiconductor substrate of p? type. A first buried impurity region of n+ type is formed at an interface between the semiconductor substrate and the semiconductor layer. A second buried impurity region of p+ type is formed at an interface between the first buried impurity region and the semiconductor layer. Above the first and second buried impurity regions, a first impurity region of n type is formed in an upper surface of the semiconductor layer. Above the first and second buried impurity regions, a second impurity region of p type is also formed apart from the first impurity region in the upper surface of the semiconductor layer. When the second impurity region becomes higher in potential than the first impurity region, the second impurity region and the second buried impurity region are electrically isolated from each other by a depletion layer.

Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.

Abstract: In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring. A substrate resistance determination system is associated with the electrostatic discharge protection device to determine a substrate resistance distribution at the transistor-formation area such that snapbacks occur in all the fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.

Abstract: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

Abstract: In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell. The intermediate potential electrode (20) is supplied with a prescribed intermediate potential between the potentials at an emitter electrode (10) and a channel stopper electrode (12) from intermediate potential applying means that is formed locally in a partial region on the chip peripheral portion.

Abstract: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region.

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: A semiconductor device has a first region and a second region formed on a surface of a substrate. Plural first conductors and second conductors are formed in the first and second regions respectively. A first semiconductor region and a second semiconductor region are formed between adjacent first conductors. The second semiconductor region is in the first semiconductor region and has a conductivity type opposite to that of the first semiconductor. A third semiconductor region is formed between adjacent second conductors. The third semiconductor region has the same conductivity type as the second semiconductor region and is lower in density than the second semiconductor region. The third semiconductor region has a metal contact region for contact with a metal, which is electrically connected to the second semiconductor region. A center-to-center distance between adjacent first conductors is smaller than that between adjacent second conductors.

Abstract: A semiconductor device 1 includes a square substrate 2, first RESURF structures 3 in the shape of planar stripes on an element area 10 of a main surface of the substrate 2, a transistor T arranged between the first RESURF structures 3, a first high withstand voltage section 11 constituted by second RESURF structures 3a in the shape of planar strips on a periphery of the main surface of the substrate 2, and a second high withstand voltage section 12 constituted by third RESURF structures 3b which are symmetrically arranged at corners of the substrate 2 with respect to a diagonal line D of the main surface of the substrate 2.

Abstract: A high-voltage transistor device has a first well region with a first conductivity type in a semiconductor substrate, and a second well region with a second conductivity type in the semiconductor substrate substantially adjacent to the first well region. A field ring with the second conductivity type is formed on a portion of the first well region, and the top surface of the field ring has at least one curved recess. A field dielectric region is formed on the field ring and extends to a portion of the first well region. A gate structure is formed over a portion of the field dielectric region and extends to a portion of the second well region.

Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

Abstract: A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.