Abstract: A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film, the first film having a first portion connected to the substrate, a second portion located above the sacrificial film, a third portion located between the first portion and the second portion, and a thin region in a portion of the third portion or in a boundary section between the second portion and the third portion and having a thickness smaller than the first portion; (c) removing the sacrificial film; and (d) bending the first film in the thin region, after the step (c), thereby sloping the second portion of the first film with respect to the substrate.

Abstract: Provided is a biological component detection device with which a biological component can be detected at high sensitivity by using an InP-based photodiode in which a dark current is reduced without using a cooling mechanism and the sensitivity is extended to a wavelength of 1.8 ?m or more. An absorption layer 3 has a multiple quantum well structure composed of group III-V semiconductors, a pn-junction 15 is formed by selectively diffusing an impurity element in the absorption layer, and the concentration of the impurity element in the absorption layer is 5×1016/cm3 or less, the diffusion concentration distribution control layer has an n-type impurity concentration of 2×1015/cm3 or less before the diffusion, the diffusion concentration distribution control layer having a portion adjacent to the absorption layer, the portion having a low impurity concentration.

Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.

Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.

Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.

Abstract: According to one embodiment, a template substrate includes a substrate and a mask. The substrate includes a mesa region formed in a central portion of an upper surface of the substrate. The mesa region is configured to protrude more than a region of the substrate around the mesa region. An impurity is introduced into an upper layer portion of a partial region of a peripheral portion of the mesa region. The mask film is provided on the upper surface of the substrate.

Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.

Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.

Abstract: Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.

Abstract: A cuboidal protuberant structure is provided. The cuboidal protuberant structure includes a substrate and a protrusion disposed on the substrate. The protrusion has a vertical side wall with a rounded corner, a protuberant width and a protuberant length. At least one of the protuberant width and the protuberant length is not greater than 33 nm.

Abstract: The invention relates to a method for manufacturing a semiconductor substrate by providing a seed support layer and a handle support layer, forming at least one semiconductor layer, in particular of a Group III/V-semiconductor material, over the seed support layer, wherein the at least one semiconductor layer is in a strained state, forming a bonding layer over the at least one semiconductor layer, forming a bonding layer over the handle support layer, and bonding the seed and handle substrates together to obtain a donor-handle compound, by direct bonding between the bonding layer of the seed substrate and the bonding layer of the handle substrate. At least one of the bonding layer of the seed substrate and the bonding layer of the handle substrate includes a silicon nitride.

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Abstract: An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the changed defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.

Abstract: Processes for making a membrane having a curved feature are disclosed. Recesses each in the shape of a reversed, truncated pyramid are formed in a planar substrate surface by KOH etching through a mask. An oxide layer is formed over the substrate surface. The oxide layer can be stripped leaving rounded corners between different facets of the recesses in the substrate surface, and the substrate surface can be used as a profile-transferring substrate surface for making a membrane having concave curved features. Alternatively, a handle layer is attached to the oxide layer and the substrate is removed until the backside of the oxide layer becomes exposed. The exposed backside of the oxide layer includes curved portions protruding away from the handle layer, and can provide a profile-transferring substrate surface for making a membrane having convex curved features.

Abstract: A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.

Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Abstract: A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.

Abstract: The present invention provides a method for selectively transferring elements such as monocrystalline Si thin films or elements made of monocrystalline Si from a base substrate (100) onto an insulating substrate without the use of an intermediate substrate. The base substrate (first substrate) (100) in which the elements are formed is selectively irradiated with a laser having a multiphoton absorption wavelength. Thus, elements to be transferred out of the elements and corresponding thin films on the base substrate (100) are transferred onto a transfer destination substrate (second substrate) (200).

Abstract: A silicon layer transfer substrate includes a silicon substrate of a first substrate, a sacrificial layer, and a transfer silicon layer transferred to a second substrate, wherein the sacrificial layer has a silicon compound layer containing a compound of silicon and at least one element selected from a group consisting of germanium and carbon, and is provided on the silicon substrate of the first substrate, the silicon compound layer having a thickness equal to or smaller than a critical film thickness, the transfer silicon layer transferred to the second substrate is provided on the sacrificial layer, and at least either the silicon substrate or the silicon layer has a groove or a hole connected to the sacrificial layer.

Abstract: A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused.

Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

Abstract: A semiconductor device includes: a fin-type semiconductor region (13) formed on a substrate (11); a gate insulating film (14) formed so as to cover an upper surface and both side surfaces of a predetermined portion of the fin-type semiconductor region (13); a gate electrode (15) formed on the gate insulating film (14); and an impurity region (17) formed on both sides of the gate electrode (15) in the fin-type semiconductor region (13). An impurity blocking portion (15a) for blocking the introduction of impurities is provided adjacent both sides of the gate electrode (15) over an upper surface of the fin-type semiconductor region (13).

Abstract: A semiconductor device includes a first non-flat non-polar nitride semiconductor layer, a first structure layer on at least a portion of the surface of the first non-flat non-polar nitride semiconductor layer and a first non-polar nitride semiconductor layer on the first non-flat non-polar nitride semiconductor layer and the first structure layer. The first non-flat non-polar nitride semiconductor layer includes a plurality of solid particles.

Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.

Abstract: A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a steering element above a substrate; and (2) fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (CNT) material above the substrate. Numerous other aspects are provided.

Abstract: To provide a method of manufacturing a semiconductor device with reduced generation of humps, a semiconductor device with reduced generation of humps, and a resist coater. An inactive liquid such as pure water is discharged at a predetermined pressure from a nozzle for discharging fluid for processing hump while spinning the semiconductor substrate to spray a region where a hump is generated. The hump is crushed by spraying the inactive liquid at a high pressure onto the hump, and the film thickness of the bottom-layer resist becomes almost uniform across the entire semiconductor substrate.

Abstract: An embodiment of nanostructure includes a conductive substrate; an insulating layer on the conductive substrate, metal nanoparticles, and elongated single crystal nanostructures. The insulating layer includes an array of pore channels. The metal nanoparticles are located at bottoms of the pore channels. The elongated single crystal nanostructures contact the metal nanoparticles and extend out of the pore channels. An embodiment of a photovoltaic device includes the nanostructure and a photoabsorption layer. An embodiment of a method of fabricating a nanostructure includes forming an insulating layer on a conductive substrate. The insulating layer has pore channels arranged in an array. Metal nanoparticles are formed in the pore channels. The metal nanoparticles conductively couple to the conductive layer. Elongated single crystal nanostructures are formed in the pore channels.

Abstract: The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.

Abstract: A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Abstract: A plurality of core-shell semiconductor nanowires each being fixed to a support includes II-VI materials for both the cores and the shells. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.

Abstract: A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.

Abstract: A superlattice-based infrared absorber and the matching electron-blocking and hole-blocking unipolar barriers, absorbers and barriers with graded band gaps, high-performance infrared detectors, and methods of manufacturing such devices are provided herein. The infrared absorber material is made from a superlattice (periodic structure) where each period consists of two or more layers of InAs, InSb, InSbAs, or InGaAs. The layer widths and alloy compositions are chosen to yield the desired energy band gap, absorption strength, and strain balance for the particular application. Furthermore, the periodicity of the superlattice can be “chirped” (varied) to create a material with a graded or varying energy band gap.

Abstract: A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

Abstract: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.

Abstract: A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip (21), when viewed from a direction perpendicular to the semiconductor chip (21), has a rectangular shape that has a first side (1A) and a second side (1B) orthogonal to the first side (1A). The amount of thermal deformation along a direction in which the first side (1A) extends and the amount of thermal deformation along a direction in which the second side (1B) extends are substantially equal to each other.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: Provided are a light-receiving element which has sensitivity in the near-infrared region and in which a good crystal quality is easily obtained, a one-dimensional or two-dimensional array of the light-receiving elements is easily formed with a high accuracy, and a dark current can be reduced; a light-receiving element array; and methods for producing the same. A light-receiving element includes a group III-V compound semiconductor stacked structure including an absorption layer 3 having a pn-junction 15 therein, wherein the absorption layer has a multiquantum well structure composed of group III-V compound semiconductors, the pn-junction 15 is formed by selectively diffusing an impurity element into the absorption layer, and the concentration of the impurity element in the absorption layer is 5×1016 cm?3 or less.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.

Abstract: A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where the fins need to be broadened and a second area is defined where the fins do not need to be broadened. The method also includes patterning the spacer layer to remove spacers in the first area where the fins need to be broadened and applying an epitaxy process at a predetermined rate to grow a layer of the first material on fins in the first area. The spacer layer is removed in the second area where the fins do not need broadening.

Abstract: A semiconductor device (10), comprising a first semiconductor portion (32) having a first end (34), a second end (36), and a slit portion (30), wherein the width of the slit portion (30) is less than the width of at least one of the first end (34) and the second end (36); a second portion (38) that is a different material than the first semiconductor portion (32), a third portion (40) that is a different material than the first semiconductor portion (32), wherein the second (38) and third (40) portions are on opposite sides of the slit portion (30), and at least three terminals selected from a group consisting of a first terminal (12) connected to the first end (34), a second terminal (14) connected to the second end (36), a third terminal (16) connected to the second portion (38), and a fourth terminal (17) connected to the third portion (40).

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract: Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product.

Abstract: Methods synthesizing nanowires in solution at low temperatures (e.g., about 400° C. or lower) are provided. In the present methods, the nanowires are synthesized by exposing nanowire precursors to metal nanocrystals in a nanowire growth solution comprising a solvent. The metal nanocrystals serve as seed particles that catalyze the growth of the semiconductor nanowires. The metal nanocrystals may be formed in situ in the growth solution from metal nanocrystal precursors. Alternatively, the nanowires may be pre-formed and added to the growth solution.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area.