Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

Abstract: A method of fabricating a device on a substrate includes doping a channel region of the device with dopants. The method further includes growing an undoped epitaxial layer over the channel region, wherein growing the undoped epitaxial layer comprises deactivating dopants in the channel region to form a deactivated region. The method further includes forming a gate structure over the deactivated region.

Abstract: Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.

Abstract: An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.

Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

Abstract: A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene

Abstract: According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.

Abstract: An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.

Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

Abstract: A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

Abstract: An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

Abstract: Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

Abstract: A semiconductor device includes a first electrode on a semiconductor element at a first location and a second electrode on the semiconductor element at a second location spaced from the first location. And insulating film covers the first electrode, the second electrode and a third electrode. First and second pads are on the insulating film. The first electrode contacts the first pad through an opening in a first portion of the insulating film. The second electrode contacts the second pad each through an opening in a second portion of the insulating film. A bonding surface of the first pad is at a first distance above one portion of the insulating film, and a second distance above another. A bonding surface of the second pad likewise at different distances above the insulating film depending on location.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

Abstract: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.

Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.

Abstract: A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.