Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.

Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: A pinned photodiode sensor with gate-controlled SCR switch includes a pinned photodiode and a gate-controlled SCR switch. The SCR switch includes a P-type substrate, an N? doped region, and an N+ doped region formed on the substrate; a P+ doped region formed on the N? doped region; an oxide layer formed on the P substrate, the N? doped region, the N+ doped region, and the P+ doped region; and a gate formed above the P substrate and the N? doped region. The gate includes a P+ doped region and an N+ doped region. During an exposure procedure, a depletion region will not reach the interface between the oxide layer and the substrate, thereby preventing dark current leakage.

Abstract: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.

Abstract: Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.

Abstract: A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.