Compositional Structures (epo) Patents (Class 257/E29.075)
  • Publication number: 20140117311
    Abstract: Semiconductor structures having a nanocrystalline core and nanocrystalline shell pairing compositional transition layers are described. In an example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A compositional transition layer is disposed between, and in contact with, the nanocrystalline core and nanocrystalline shell and has a composition intermediate to the first and second semiconductor materials. In another example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A nanocrystalline outer shell surrounds the nanocrystalline shell and is composed of a third semiconductor material.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Inventor: Juanita N. Kurtin
  • Patent number: 8421058
    Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure includes a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer including the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 16, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Wei Liu, Chew Beng Soh, Soo Jin Chua, Jing Hua Teng
  • Publication number: 20130043459
    Abstract: An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide antimonide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 21, 2013
    Applicant: SVT ASSOCIATES, INC.
    Inventors: Yiqiao Chen, Peter Chow
  • Publication number: 20130009132
    Abstract: Embodiments of a material having low cross-plane thermal conductivity are provided. Preferably, the material is a thermoelectric material. In general, the thermoelectric material is designed to block phonons, which reduces or eliminates heat transport due to lattice vibrations and thus cross-plane thermal conductivity. By reducing the thermal conductivity of the thermoelectric material, a figure-of-merit (ZT) of the thermoelectric material is improved. In one embodiment, the thermoelectric material includes multiple superlattice periods that block, or reflect, multiple phonon wavelengths.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 10, 2013
    Applicant: THE BOARD OF REGENTS OF THE UNIVERSITY OF OKLAHOMA
    Inventor: Patrick John McCann
  • Patent number: 8247793
    Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: August 21, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Ken Nakahara, Shunsuke Akasaka, Masashi Kawasaki, Akira Ohtomo, Atsushi Tsukazaki
  • Patent number: 8188458
    Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 29, 2012
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Stacia Keller, Steven P. DenBaars, Tal Margalith, James S. Speck, Shuji Nakamura, Umesh K. Mishra
  • Publication number: 20110220874
    Abstract: A nanostructured composite material comprising semiconductor nanocrystals in a crystalline semiconductor matrix. Suitable nanocrystals include silicon, germanium, and silicon-germanium alloys, and lead salts such as PbS, PbSe, and PbTe. Suitable crystalline semiconductor matrix materials include Si and silicon-germanium alloys. A process for making the nanostructured composite materials. Devices comprising nanostructured composite materials.
    Type: Application
    Filed: August 10, 2009
    Publication date: September 15, 2011
    Inventors: Tobias Hanrath, James R. Engstrom
  • Publication number: 20110204329
    Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Michael D. Craven, Stacia Keller, Steven P. DenBaars, Tal Margalith, James Stephen Speck, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 7977666
    Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: July 12, 2011
    Assignee: Academia Sinica
    Inventors: Shiang-Yu Wang, Hong-Shi Ling, Ming-Cheng Lo, Chien-Ping Lee
  • Publication number: 20110094582
    Abstract: Provided is an electrode including a conductive surface connected to a matrix; the matrix including a plurality of semiconductor nanoparticles and noble metal nanoparticles, substantially each of which is connected to another nanoparticle of the plurality of nanoparticles by at least one matrix connecting group and at least a portion of the plurality of nanoparticles of the matrix is each connected to the conductive surface by at least one surface connecting group. Further provided are photovoltaic cells and devices including electrode of the invention.
    Type: Application
    Filed: June 28, 2009
    Publication date: April 28, 2011
    Applicant: Yissum Research Development Company of the Hebrew University of Jerusalem, Ltd.
    Inventors: Itamar Willner, Ran Tel-Vered, Huseyin Bekir Yildiz
  • Patent number: 7812339
    Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Kalipatnam Vivek Rao
  • Patent number: 7781827
    Abstract: A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: August 24, 2010
    Assignee: Mears Technologies, Inc.
    Inventor: Kalipatnam Vivek Rao
  • Patent number: 7700936
    Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 20, 2010
    Assignee: University of Delaware
    Inventors: Janusz Murakowski, Garrett Schneider, Dennis W. Prather
  • Patent number: 7649212
    Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: January 19, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Luc Morand
  • Publication number: 20090053536
    Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.
    Type: Application
    Filed: October 29, 2008
    Publication date: February 26, 2009
    Inventors: Klaus KUNZE et al., Scott Haubrich, Fabio Zurcher, Brent Ridley, Joerg Rockenberger
  • Publication number: 20090032801
    Abstract: An in situ approach toward connecting and electrically contacting vertically aligned nanowire arrays using conductive nanoparticles is provided. The utility of the approach is demonstrated by development of a gas sensing device employing the nanowire assembly. Well-aligned, single-crystalline zinc oxide nanowires were grown through a direct thermal evaporation process at 550° C. on gold catalyst layers. Electrical contact to the top of the nanowire array was established by creating a contiguous nanoparticle film through electrostatic attachment of conductive gold nanoparticles exclusively onto the tips of nanowires. A gas sensing device was constructed using such an arrangement and the nanowire assembly was found to be sensitive to both reducing (methanol) and oxidizing (nitrous oxides) gases. This assembly approach is amenable to any nanowire array for which a top contact electrode is needed.
    Type: Application
    Filed: April 29, 2008
    Publication date: February 5, 2009
    Applicant: University of Maryland
    Inventors: Prahalad Parthangal, Michael R. Zachariah, Richard E. Cavicchi
  • Publication number: 20080157057
    Abstract: Disclosed are a nanostructure with an indium gallium nitride quantum well and a light emitting diode employing the same. The light emitting diode comprises a substrate, a transparent electrode and an array of nanostructures interposed between the substrate and the transparent electrode. Each of the nanostructures comprises a core nanorod, and a nano shell surrounding the core nanorod. The core nanorod is formed substantially perpendicularly to the substrate and includes a first nanorod of a first conductivity type, an (AlxInyGa1-x-y)N (where, 0?x?1, 0?y?1 and 0?x+y?1) quantum well, and a second nanorod of a second conductivity type, which are joined in a longitudinal direction. The nano shell is formed of a material with a bandgap greater than that of the quantum well, and surrounds at least the quantum well of the core nanorod. Meanwhile, the second nanorods are connected in common to the transparent electrode.
    Type: Application
    Filed: June 25, 2005
    Publication date: July 3, 2008
    Applicant: SEOUL OPTO DEVICE CO., LTD
    Inventor: Hwa Mok Kim