Abstract: An (AlInGaN) based semiconductor device, including one or more (In,Al)GaN layers overlying a semi-polar or non-polar III-nitride substrate or buffer layer, wherein the substrate or buffer employs patterning to influence or control extended defect morphology in layers deposited on the substrate; and one or more (AlInGaN) device layers above and/or below the (In,Al)GaN layers.

Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure includes a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer including the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.

Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.

Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.

Abstract: The semiconductor layer structure includes an active layer and a superlattice composed of stacked layers of III-V compound semiconductors of a first and at least one second type. Adjacent layers of different types in the superlattice differ in composition with respect to at least one element. The layers have predefined layer thicknesses, such that the layer thicknesses of layers of the first type and of the layers of the second type increase from layer to layer with increasing distance from an active layer. An increasing layer thickness within the layers of the first and the second type is suitable for adapting the electrical, optical and epitaxial properties of the superlattice to given requirements in the best possible manner.

Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.

Abstract: An optical semiconductor device includes a substrate; and an active layer disposed on the substrate, wherein the active layer includes a first barrier layer containing GaAs, a quantum dot layer, which is disposed on the first barrier layer, which includes a quantum dot containing InAs, which includes a side barrier layer which covers at least a part of the quantum dot and a side surface of the quantum dot, and having an elongation strain inherent therein, and a second barrier layer disposed on the quantum dot layer.

Abstract: A light-emitting device includes a substrate, a first doped semiconductor layer situated above the substrate, a second doped semiconductor layer situated above the first doped layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped layer and a first passivation layer situated between the first electrode and the first doped layer in areas other than an ohmic-contact area. The first passivation layer substantially insulates the first electrode from edges of the first doped layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped layer and a second passivation layer which substantially covers the sidewalls of the first and second doped layers, the MQW active layer, and the horizontal surface of the second doped layer.

Abstract: A semiconductor nanocrystal heterostructure has a core of a first semiconductor material surrounded by an overcoating of a second semiconductor material. Upon excitation, one carrier can be substantially confined to the core and the other carrier can be substantially confined to the overcoating.

Abstract: A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract: A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 ?. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.

Abstract: A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract: Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained.

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.

Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.

Abstract: A QWIP structure is disclosed that includes a graded emitter barrier and can further be configured with a blocked superlattice miniband. The graded emitter barrier effectively operates to launch dark electrons into the active quantum well region, thereby improving responsivity. A graded collector barrier may also be included for reverse bias applications. The configuration operates to eliminate or otherwise reduce image artifacts or persistence associated with dielectric relaxation effect in low-background applications.

Abstract: The semiconductor layer structure includes a superlattice (9) composed of stacked layers (9a, 9b) of III-V compound semiconductors of a first (a) and at least one second type (b). Adjacent layers of different types in the superlattice (9) differ in composition with respect to at least one element, at least two layers of the same type have a different content (cAl, cIn) of the at least one element, the content (cAl, cIn) of the at least one element is graded within a layer (9a, 9b) of the superlattice (9), and the layers (9a, 9b) of the superlattice contain dopants in predefined concentrations, with the superlattice (9) comprising layers (9a, 9b) that are doped with different dopants. In this way, the electrical, optical and epitaxial properties of the superlattice (9) can be adapted in the best possible manner to given requirements, particularly epitaxial constraints.

Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.

Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.

Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.

Abstract: A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second layer having the other horizontal surface; an insulator support between the first layer and the second layer that separates the first layer from the second layer. A portion of the second layer overhangs the insulator support, such that the horizontal surface of the overhanging portion is spaced from and faces the (111) horizontal surface of the first layer. The structure further includes a nanowire column extending nearly vertically from the (111) horizontal surface to the facing horizontal surface, such that the nanowire column connects the first layer to the second layer.