Structures With Periodic Or Quasi-periodic Potential Variation, (e.g., Multiple Quantum Wells, Superlattices) (epo) Patents (Class 257/E29.072)
  • Patent number: 9029916
    Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hoon Lee, Ki-se Kim
  • Patent number: 8981344
    Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 17, 2015
    Inventors: Faquir Chand Jain, Evan Heller
  • Patent number: 8957432
    Abstract: A semiconductor device may reduce a dislocation density and tensile stress by forming a plurality of interlayers between neighboring clad layers. The semiconductor device may include a plurality of clad layers on a substrate and a plurality of interlayers between neighboring clad layers.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Young-jo Tak, Jae-won Lee
  • Patent number: 8946679
    Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventor: Ravi Pillarisetty
  • Patent number: 8890113
    Abstract: A light-emitting device epitaxially-grown on a GaAs substrate which contains an active region composed of AlxGa1-xAs alloy or of related superlattices of this materials system is disclosed. This active region either includes tensile-strained GaP-rich insertions aimed to increase the forbidden gap of the active region targeting the bright red, orange, yellow, or green spectral ranges, or is confined by regions with GaP-rich insertions aimed to increase the barrier height for electrons in the conduction band preventing the leakage of the nonequilibrium carriers outside of the light-generation region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 18, 2014
    Inventors: Nikolay Ledentsov, James Lott, Vitaly Shchukin
  • Patent number: 8816320
    Abstract: A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: August 26, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Sho Iwayama, Masahiko Moteki
  • Patent number: 8785907
    Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van H. Le, Matthew V. Metz, Jack T. Kavalieros, Ravi Pillarisetty, Sanaz K. Gardner, Sansaptak Dasgupta, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic, Gilbert Dewey, Marc C. French, Jessica Kachian, Satyarth Suri, Robert S. Chau
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8680509
    Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1-xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Patent number: 8633092
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8629422
    Abstract: The method utilizes a conducting trench base with non-conducting trench walls to corral charged particles precisely into the trenches. The nanoparticles are close packed in the channels and highly ordered. This approach utilizes the charge on the particles to selectively deposit them within the trenches, as all nanoparticles in solution can be charged, and this can be extended to any nanoparticle system beyond gold. Also, this method results in the layer-by-layer growth of the gold nanoparticles. Therefore the depth of the nanoparticle layers within the trenches is controllable. This allows the possibility of heterolayered structures of different nanoparticle layers. Further this method ensures that assembly occurs to fill the void space available provided the back-contacting electrode is more conducting than the trench walls. This allows nanoparticle assemblies to be corralled into any lithographically defined shape, which makes this approach highly adaptable to a range of applications.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: January 14, 2014
    Assignee: University of Limerick
    Inventors: Kevin M. Ryan, Shafaat Ahmed
  • Publication number: 20140008613
    Abstract: A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 9, 2014
    Applicant: PHOSTEK, INC.
    Inventors: Jinn Kong Sheu, Wei-Chih Lai
  • Patent number: 8586964
    Abstract: Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: November 19, 2013
    Assignee: Korea Institute of Science and Technology
    Inventors: Jin-Dong Song, Sang Hoon Shin, Hyung-jun Kim, Hyun Cheol Koo, Suk Hee Han, Joonyeon Chang
  • Publication number: 20130265031
    Abstract: A nanogap sensor includes a first layer in which a micropore is formed; a graphene sheet disposed on the first layer and including a nanoelectrode region in which a nanogap is formed, the nanogap aligned with the micropore; a first electrode formed on the grapheme sheet; and a second electrode formed on the graphene sheet, wherein the first electrode and the second electrode are connected to respective ends of the nanoelectrode region.
    Type: Application
    Filed: September 6, 2012
    Publication date: October 10, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeo-young SHIM, Tae-han JEON, Kun-sun EOM, Dong-ho LEE, Hee-jeong JEONG, Seong-ho CHO
  • Patent number: 8541771
    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Publication number: 20130140523
    Abstract: An apparatus includes a substrate, a sequence of crystalline semiconductor layers on a planar surface of the substrate, and first and second sets of electrodes over the sequence. The sequence has a 2D quantum well therein. The first set of electrodes border opposite sides of a lateral region of the sequence and are controllable to vary a width of a non-depleted portion of the quantum well along the top surface. The second set of electrodes border channels between the lateral region and first and second adjacent lateral areas of the sequence and are controllable to vary widths of non-depleted segments of the quantum well in the channels. The electrodes are such that straight lines connecting the lateral areas via the channels either pass between one of the electrodes and the substrate or are misaligned to an effective [1 10] lattice direction of the sequence.
    Type: Application
    Filed: January 12, 2012
    Publication date: June 6, 2013
    Inventor: Robert L. Willett
  • Patent number: 8421058
    Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure includes a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer including the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 16, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Wei Liu, Chew Beng Soh, Soo Jin Chua, Jing Hua Teng
  • Patent number: 8405064
    Abstract: An inventive nitride semiconductor device includes: a substrate; a first buffer layer provided on the substrate, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; a second buffer layer provided on the first buffer layer in contact with the first buffer layer, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; and a device operation layer of a Group III nitride semiconductor provided on the second buffer layer; wherein an average lattice constant LC1 of the first buffer layer, an average lattice constant LC2 of the second buffer layer and an average lattice constant LC3 of the device operation layer satisfy the following expression (1): LC1<LC2<LC3??(1).
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: March 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Atsushi Yamaguchi, Norikazu Ito, Shinya Takado
  • Patent number: 8405067
    Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Jun Shimizu, Shinichi Kohda, Yasuhiro Yamada, Naohide Wakita, Masahiro Ishida
  • Publication number: 20130049007
    Abstract: A wide-bandgap semiconductor device includes: a semiconductor substrate made of a semiconductor material having a bandgap larger than 1.42 eV; a semiconductor layer on the semiconductor substrate and made of a semiconductor material having a bandgap larger than 1.42 eV; and an active region in the semiconductor layer and including a transistor, wherein the wide-bandgap semiconductor device is opaque to light in a visible light wavelength range, from a wavelength of 360 nm to a wavelength of 830 nm.
    Type: Application
    Filed: April 2, 2012
    Publication date: February 28, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hajime SASAKI
  • Publication number: 20130032781
    Abstract: Provided is a crack-free epitaxial substrate with reduced warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a superlattice layer group in which a plurality of superlattice layers are laminated, and a crystal layer. The superlattice layer is formed of a first unit layer and a second unit layer made of group-III nitrides having different compositions being alternately and repeatedly laminated. The crystal layer is made of a group-III nitride and formed above the base substrate so as to be positioned at an upper side of the superlattice layer group relative to the base substrate. The superlattice layer group has a compressive strain contained therein. In the superlattice layer group, the more distant the superlattice layer is from the base substrate, the greater the compressive strain becomes.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 7, 2013
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto MIYOSHI, Shigeaki Sumiya, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Publication number: 20130026444
    Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
    Type: Application
    Filed: October 8, 2012
    Publication date: January 31, 2013
    Applicants: TEXAS INSTRUMENTS, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: BOARD OF REGENTS, THE UNIVERSITY OF TE, TEXAS INSTRUMENTS, INC.
  • Patent number: 8362461
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: January 29, 2013
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Publication number: 20130019932
    Abstract: Disclosed are a nanostructure array substrate, a method for fabricating the same, and a dye-sensitized solar cell by using the same. The nanostructure array substrate includes a plurality of metal oxide nanostructures vertically aligned on the substrate while being separated from each other. The metal oxide nanostructures include nanorods having a ZnO core/TiO2 shell structure or TiO2 nanotubes. The method includes the steps of forming ZnO nanorods vertically aligned from a seed layer formed on a substrate; and coating a TiO2 sol on the ZnO nanorods and sintering the ZnO nanorods to form nanorods having a ZnO core/TiO2 shell structure. The transparency and flexibility of the substrate are ensured. The photoelectric conversion efficiency of the solar cell is improved if the nanostructure array substrate is employed in the photo electrode of the dye-sensitized solar cell.
    Type: Application
    Filed: December 14, 2011
    Publication date: January 24, 2013
    Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gun Young JUNG, Hui SONG, Ki Seok KIM
  • Patent number: 8357922
    Abstract: A nanodevice, a transistor including the nanodevice, a method of manufacturing the nanodevice, and a method of manufacturing the transistor including the nanodevice are provided. The nanodevice includes a substrate, a mask layer located on the substrate and having at least one opening, and a nanotube formed on the substrate through the opening along an edge of the opening. The nanotube extends through the opening in a direction substantially perpendicular to a surface of the substrate.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: January 22, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Joon Hong, Gyu-Chul Yi
  • Publication number: 20120298958
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Application
    Filed: August 9, 2012
    Publication date: November 29, 2012
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Patent number: 8304758
    Abstract: Preparation of oxidation-reduction (redox) nano-medicine quantum dot room temperature superconductor quantum bit (qubit) networks includes processes of making unitary, binary, ternary, an d/or quaternary liquid pharmaceutical ingredients of an antioxidase antioxidant, a ?-adrenergic receptor agonist, a P2-purinergic receptor agonist, and/or a phenylalkylamine calcium channel blocker in combination with either 1:20 xanthine oxidase (XO):xanthine (X) or X alone in a liquid phase by using the L16(2)15 and L9(3)4 orthogonal optimization design protocols and modulating spatial distance constraint from about 0.1 ? to about 200 ? as well as a 10 class clean bottom-up self-assembly approach.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 6, 2012
    Assignee: Zhongshan Hospital, Fudan University
    Inventor: Yan Fang
  • Patent number: 8294137
    Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: October 23, 2012
    Inventors: Faquir Chand Jain, Evan Heller
  • Patent number: 8279904
    Abstract: A semiconductor light-emitting device including an active layer is provided. The light-emitting device includes an active layer between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes a quantum well layer formed of Inx1Ga(1?x1)N, where 0<x1?1, barrier layers formed of Inx2Ga(1?x2)N, where 0?x2<1, on opposite surfaces of the quantum well layer, and a diffusion preventing layer formed between the quantum well layer and at least one of the barrier layers. Due to the diffusion preventing layer between the quantum well layer and the barrier layers in the active layer, the light emission efficiency increases.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tan Sakong, Joong-kon Son, Ho-sun Paek, Sung-nam Lee
  • Publication number: 20120241723
    Abstract: An optoelectronic device includes a first electrode, a quantum dot layer disposed on the first electrode including a plurality of quantum dots, a fullerene layer disposed directly on the quantum dot layer wherein the quantum dot layer and the fullerene layer form an electronic heterojunction, and a second electrode disposed on the fullerene layer. The device may include an electron blocking layer. The quantum dot layer may be modified by a chemical treatment to exhibit in creased charge carrier mobility.
    Type: Application
    Filed: September 29, 2010
    Publication date: September 27, 2012
    Applicant: RESEARCH TRIANGLE INSTITUTE, INTERNATIONAL
    Inventors: Ethan Klem, John Lewis
  • Patent number: 8269209
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Uday Shah, Benjamin Chu-Kung, Been Y. Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
  • Publication number: 20120211725
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Application
    Filed: March 15, 2011
    Publication date: August 23, 2012
    Applicant: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8247793
    Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: August 21, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Ken Nakahara, Shunsuke Akasaka, Masashi Kawasaki, Akira Ohtomo, Atsushi Tsukazaki
  • Publication number: 20120175594
    Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Zhihong Chen, Aaron Daniel Franklin, Shu-Jen Han
  • Publication number: 20120175589
    Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1?xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.
    Type: Application
    Filed: August 23, 2010
    Publication date: July 12, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Publication number: 20120161105
    Abstract: A planar or non-planar quantum well device and a method of forming the quantum well device. The device includes: a buffer region comprising a large band gap material; a uniaxially strained quantum well channel region on the buffer region; an upper barrier region comprising a large band gap material on the quantum well channel region; a gate dielectric on the quantum well channel region; a gate electrode on the gate dielectric; and recessed source and drain regions at respective sides of the gate electrode, the source and drain regions including a junction material having a lattice constant different from a lattice constant of a material of the buffer region. Preferably, the buffer region comprises a Si1-xGex material, and the junction material comprises one of a Si1-yGey material where y is larger than x, or pure germanium, or tin germanium.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le
  • Publication number: 20120153261
    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.
    Type: Application
    Filed: June 10, 2011
    Publication date: June 21, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Publication number: 20120145997
    Abstract: A hot filament chemical vapor deposition method has been developed to grow at least one vertical single-walled carbon nanotube (SWNT). In general, various embodiments of the present invention disclose novel processes for growing and/or producing enhanced nanotube carpets with decreased diameters as compared to the prior art.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 14, 2012
    Applicant: William Marsh Rice University
    Inventors: Robert H. Hauge, Ya-Qiong Xu
  • Publication number: 20120132892
    Abstract: Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used.
    Type: Application
    Filed: May 27, 2010
    Publication date: May 31, 2012
    Applicant: SNU R&DB FOUNDATION
    Inventors: Gyu-chul Yi, Yong-Jin Kim
  • Patent number: 8178863
    Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: May 15, 2012
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: William E. Tennant, Gerard J. Sullivan, Mark Field
  • Publication number: 20120104358
    Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 3, 2012
    Inventor: L. Pierre de Rochemont
  • Publication number: 20120104360
    Abstract: An (AlInGaN) based semiconductor device, comprising a first layer that is a semipolar or nonpolar nitride (AlInGaN) layer having a lattice constant that is partially or fully relaxed, deposited on a substrate or a template, wherein there are one or more dislocations at a heterointerface between the first layer and the substrate or the template; one or more strain compensated layers on the first layer, for defect reduction and stress engineering in the device, that is lattice matched to a larger lattice constant of the first layer; and one or more nonpolar or semipolar (AlInGaN) device layers on the strain compensated layers.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 3, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Matthew T. Hardy, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20120080661
    Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.
    Type: Application
    Filed: August 24, 2011
    Publication date: April 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Akihiro Kajita, Atsuko Sakata
  • Publication number: 20120080662
    Abstract: According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.
    Type: Application
    Filed: August 24, 2011
    Publication date: April 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Akihiro Kajita
  • Publication number: 20120068157
    Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 22, 2012
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Francis J. Kub
  • Publication number: 20120056151
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 8, 2012
    Inventor: Chandra Mouli
  • Publication number: 20120007045
    Abstract: Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.
    Type: Application
    Filed: October 25, 2010
    Publication date: January 12, 2012
    Inventors: JIN-DONG SONG, Sang Hoon Shin, Hyung-jun Kim, Hyun Cheol Koo, Suk Hee Han, Joonyeon Chang
  • Publication number: 20120007049
    Abstract: The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.
    Type: Application
    Filed: November 2, 2010
    Publication date: January 12, 2012
    Inventors: Woo Chul JEON, Ki Yeol Park, Jung Hee Lee, Young Hwan Park
  • Publication number: 20120007050
    Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicants: THE DOSHISHA, SHOWA DENKO K.K.
    Inventors: Tadashi OHACHI, Takashi UDAGAWA
  • Publication number: 20120001153
    Abstract: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: STC. UNM
    Inventors: Stephen D. Hersee, Xin Wang, Xinyu Sun