Abstract: A thin film transistor (TFT), including a substrate, a gate electrode on the substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain electrodes in contact with the source and drain regions of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer has a GaInZnO (GIZO) bilayer structure including a lower layer and an upper layer, and the upper layer has a different indium (In) concentration than the lower layer.

Abstract: A thin film transistor according to the present invention includes: a semiconductor layer (5); a source electrode (3s) and a drain electrode (3d) that each are connected to the semiconductor layer (5); an insulating layer (6) that is formed adjacent to the semiconductor layer (5); and a gate electrode (7) that faces the semiconductor layer (5) across the insulating layer (6). The semiconductor layer (5) includes an aggregate of semiconductor fine particles composed of a complex oxide. The complex oxide contains zinc and at least one selected from a group consisting of indium, gallium and rhodium.

Abstract: A method of forming nanostructures using catalyst-free epitaxial growth includes depositing a first layer of a non-single crystalline material on a support structure; heating the support structure and the first layer such that a combined layer is formed; and growing a nanostructure on the combined layer. A hetero-crystalline includes a support structure; a first layer of non-single crystalline material deposited on the support structure and combined with the support structure or a second layer to form a combined layer; and a nanostructure of a single crystalline material grown on the combined layer.

Abstract: A diffusion and laser photoelectrically coupled integrated circuit signal line, wherein photoelectrically coupled pairs are formed on integrated circuit chips utilizing a diffusion light or a laser light emitted by LED or the photoelectrically coupled pairs are arranged in an array to form photoelectrically coupled matrixes on the chips are used as signal lines connecting integrated circuits; furthermore a light emission is made to hollow light emitter and placed on the integrated circuit chip; a hollow reflective sheet is located on the bottom surface of the chip and under the light emitting body where a send-receiving photosensitive module is disposed around and a hollow reflective sheet or a semitransparent diffusion sheet is placed over; and the same processed chips are stacked up. The present invention solves the problem of signal transmission bandwidth between the computer chips, increasing the present arithmetic capability and reducing the volume of the supercomputer.

Abstract: A bistable electrical device that is convertible between a low resistance state and a high resistance state. The device includes at least one layer of organic low conductivity material that is sandwiched between two electrodes. A buffer layer is located between the organic layer and at least one of the electrodes. The buffer layer includes particles in the form of flakes or dots of a low conducting material or insulating material that are present in a sufficient amount to only partially cover the electrode surface. The presence of the buffer layer controls metal migration into the organic layer when voltage pulses are applied between the electrodes to convert the device back and forth between the low and high resistance states.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Abstract: A semiconductor laser device including: semiconductor layers including an n-type semiconductor layer, an active layer and a p-type semiconductor layer, the semiconductor layers having a stripe-shaped waveguide region formed therein; end face protective film formed on the end face of the semiconductor layer that is substantially perpendicular to the waveguide region; wherein a p-side protruding portion is formed in the vicinity of the end portion of a p-electrode or n-electrode.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.