Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-germanium, zinc-lead, cadmium-germanium, cadmium-tin, cadmium-lead.

Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

Abstract: A silicon-made low-forward-voltage Schottky barrier diode is serially combined with a high-antivoltage-strength high-electron-mobility transistor made from a nitride semiconductor that is wider in bandgap than silicon. The Schottky barrier diode has its anode connected to the gate, and its cathode to the source, of the HEMT. This HEMT is normally on. The reverse voltage withstanding capability of the complete device depends upon that between the drain and gate of the HEMT.

Abstract: The present invention is directed to photonic devices which emit or absorb light with a wavelength shorter than that GaN photonic devices can emit or absorb. The devices according to the present invention are formed using molybdenum oxide of a high purity as a light emitting region or a light absorbing region. New inexpensive photonic devices which emit light with a wavelength from blue to deep ultraviolet rays are realized. The devices according to the present invention can be formed at a temperature relating low such as 700° C.

Abstract: A phase change memory and a method of manufacture are provided. The phase change memory includes a layer of phase change material treated to increase the hydrophobic nature of the phase change material. The hydrophobic nature of the phase change material improves adhesion between the phase change material and an overlying mask layer. The phase change material may be treated, for example, with a plasma comprising N2, NH3, Ar, He, O2, H2, or the like.

Abstract: Provided is a thin film transistor capable of improving reliability in the thin film transistor including an oxide semiconductor layer. A thin film transistor including: a gate electrode; a gate insulating film formed on the gate electrode; an oxide semiconductor layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective film formed at least in a region corresponding to the channel region on the oxide semiconductor layer; and a source/drain electrode. A top face and a side face of the oxide semiconductor layer are covered with the source/drain electrode and the channel protective layer on the gate insulating film.

Abstract: It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.

Abstract: An object is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. An oxide semiconductor layer including SiOx is used in a channel formation region, and in order to reduce contact resistance with source and drain electrode layers formed using a metal material with low electric resistance, source and drain regions are provided between the source and drain electrode layers and the oxide semiconductor layer including SiOx. The source and drain regions are formed using an oxide semiconductor layer which does not include SiOx or an oxynitride film.

Abstract: A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom gate configuration where both transistors share the same gate electrode. The shared gate electrode is used as a doping or implantation mask in the formation of the source and drain regions of the poly-silicon transistor.

Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Abstract: A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

Abstract: An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and a first drain. A portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal. The second transistor includes a second gate, a second oxide semiconductor layer, a second source and a second drain. A portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may have different thickness or different carrier concentrations.

Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

Abstract: A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.

Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium.

Abstract: To form an oxide semiconductor TFT having a fine property, which can be utilized for driving elements of a display, on a cheap glass substrate or a resin substrate such as PET that is light and flexible with fine regenerability and yield. Through radiating pulse light to an oxide semiconductor, a fine-quality oxide semiconductor film can be formed on a glass substrate or a resin substrate such as PET. This makes it possible to manufacture thin film devices having a fine property with fine regenerability and yield.

Abstract: Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.

Abstract: An object is to provide a semiconductor device including a thin film transistor with excellent electrical characteristics and high reliability and a method for manufacturing the semiconductor device with high mass productivity. A main point is to form a low-resistance oxide semiconductor layer as a source or drain region after forming a drain or source electrode layer over a gate insulating layer and to form an oxide semiconductor film thereover as a semiconductor layer. It is preferable that an oxygen-excess oxide semiconductor layer be used as a semiconductor layer and an oxygen-deficient oxide semiconductor layer be used as a source region and a drain region.

Abstract: Disclosed are an oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may include a lanthanoid (Ln) added to zinc oxide (ZnO) and may be used as a channel material of the TFT.

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Abstract: The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.

Abstract: In general, the invention relates to gas sensing techniques as such, but more specifically, to a sensor structure that comprises a buried electrode structure in the sensor layers, the structure being arranged to be applicable in the related devices and/or measurements. The invention relates also to a measurement method of sensor resistance, which method comprises a step of utilisation having a bias voltage or a grounding applied to the buried electrode.

Abstract: A light emitting device includes a laminate of a lower electrode layer, an organic light-emitting layer, and an upper transparent electrode layer. In the light emitting device, an auxiliary electrode layer is formed of colloidal nano-sized particles of a conductive metal between the lower electrode layer and the organic light-emitting layer. The auxiliary electrode layer causes the lower electrode layer to be flat and the light emitting efficient to be improved. A light emitting device having a structure in which a transparent electrode layer is formed as the lower electrode layer, and an organic light-emitting layer, an auxiliary electrode layer, and an upper electrode layer are sequentially formed thereon has the same effects. When glass is produced by a sol-gel method using metal alkoxide and the light emitting device is sealed by the glass, it is possible to extend the light emitting period.

Abstract: A method of dividing single crystals, particularly of plates of parts thereof, is proposed, which can comprise: pre-adjusting the crystallographic cleavage plane (2?) relative to the cleavage device, setting a tensional intensity (K) by means of tensional fields (3?, 4?), determining an energy release rate G(?) in dependence from a possible deflection angle (?) from the cleavage plane (2?) upon crack propagation, controlling the tensional fields (3?, 4?) such that the crack further propagates in the single crystal, wherein G(0)?2?e(0) and simultaneously at least one of the following conditions is satisfied: ? ? G ? ? ? ? = 0 ? 2 ? ? e h ? ? if ? ? ? 2 ? G ? ? 2 ? 0 ? ? or ( 2.1 ) ? ? G ? ? ? ? 2 ? ? e h ? ? ? ? : ? ? 1 < ? < ? 2 , ( 2.

Abstract: In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is exposed to a functionalizing material that binds to carbon atoms in the graphene sheets so that the functionalizing material remains between the graphene sheets, thereby generating a functionalized graphitic structure. The functionalized graphitic structure is dried in an inert environment.

Abstract: In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.

Abstract: A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode electrode and an anode electrode of the diode are electrically connected to the source electrode and the gate electrode of the field effect transistor, respectively.

Abstract: Provided are a display substrate and a display device including the same. The display substrate includes: gate wiring; a first semiconductor pattern formed on the gate wiring and having a first energy bandgap; a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap; data wiring formed on the first semiconductor pattern; and a pixel electrode electrically connected to the data wiring. Because the second energy bandgap is larger than the first energy bandgap, a quantum well is formed in the first semiconductor pattern, enhancing electron mobility therein.

Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.

Abstract: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.

Abstract: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.

Abstract: The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.

Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.

Abstract: A light-emitting LED device has one or more light-emitting LED elements, including first and second spaced-apart electrodes with one or more light-emitting layers formed there-between, wherein at least one of the electrodes is a transparent electrode. Also included are a first transparent encapsulating layer having a first optical index formed over the transparent electrode opposite the light-emitting layer; a light-scattering layer formed over the first transparent encapsulating layer opposite the transparent electrode; and a second transparent encapsulating layer, having a second optical index lower than the first optical index, formed over the light-scattering layer.

Abstract: An LED element having a voltage regulating capability has a body, two pins, a resistor and a conductive sleeve. The resistor is connected to a shorter pin through the conductive sleeve, so an operator can easily use the conductive sleeve to cover the shorter pin and one of two terminals of the resistor. Further, to increase connecting strength among the conductive sleeve, the shorter pin and the terminal of the resistor, an operator further uses a tongs to deform the conductive sleeve to tight the pin and the terminal.

Abstract: A semiconductor device includes a substrate, a transparent oxide layer disposed on one surface side of the substrate, a gate disposed apart from the transparent oxide layer, and a gate insulating layer disposed between the transparent oxide layer and the gate. The transparent oxide layer includes a source, a drain, and a channel formed integrally between the source and the drain, and is made of a transparent oxide material as the main material. The gate provides an electric field to the channel. The gate insulating layer insulates the source and the drain from the gate. The average thickness of the channel is smaller than the average thickness of the source and the drain so that the source and the drain function as conductors and the channel functions as a semiconductor.

Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Abstract: A light emitting device includes: a first substrate; a second substrate; a light emitting unit interposed between the first substrate and the second substrate; and a sealing material bonding the first substrate to the second substrate and sealing the light emitting unit. The sealing material comprises V+4. In addition, a glass frit, a composition for forming a sealing material, and a method of manufacturing a light emitting device using the composition for forming a sealing material are provided to obtain the light emitting device. The sealing material of the light emitting device can be easily formed by coating and irradiation of electro-magnetic waves, so that manufacturing costs are low and deterioration of the light emitting unit occurring when sealing material is formed can be substantially prevented. The sealing material has good sealing properties and thus a light emitting device including the sealing material has a long lifetime.

Abstract: To provide a Ga2O3 compound semiconductor device in which a Ga2O3 system compound is used as a semiconductor, which has an electrode having ohmic characteristics adapted to the Ga2O3 system compound, and which can make a heat treatment for obtaining the ohmic characteristics unnecessary. An n-side electrode 20 including at least a Ti layer is formed on a lower surface of an n-type ?-Ga2O3 substrate 2 by utilizing a PLD method. This n-side electrode 20 has ohmic characteristics at 25° C. The n-side electrode 20 may have two layer including a Ti layer and an Au layer, three layers including a Ti layer, an Al layer and an Au layer, or four layers including a Ti layer, an Al layer, a Ni layer and an Au layer.

Abstract: A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may be formed on a portion of the substrate. The gate insulation layer may be formed on the substrate and the gate. The channel includes ZnO and may be formed on the gate insulation layer over the gate. The source and the drain contact sides of the channel.

Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO2, or In2O3. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, SnO2 or In2O3, the substantially insulating ZnO, SnO2, or In2O3 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Abstract: A nitride semiconductor substrate having a diameter of 10 mm or more, which has a single-layer structure composed of a nitride semiconductor layer having a basic composition represented by AlxGa1?xN (0?x?1), or a multi-layer structure comprising the nitride semiconductor layer, the mass density of the nitride semiconductor layer being 98% or more of a theoretical mass density ? (x) represented by the following general formula (1): ? ? ( x ) = 4 ? ( M x + M N ) 3 ? a x 2 ? c x ? N a , ( 1 ) wherein ax=aGaN+(aAlN?aGaN)x, wherein aGaN represents an a-axis length of GaN, and aAlN represents an a-axis length of AlN; cx=cGaN+(cAlN?cGaN)x, wherein cGaN represents a c-axis length of GaN, and CAlN represents a c-axis length of AlN; Mx=MGa+(MAl?MGa)x, wherein MGa represents the atomic weight of Ga, and MAl represents the atomic weight of Al; MN represents the atomic weight of nitrogen; and Na represents Avogadro's number.