Gate Electrodes For Transistors With Floating Gate (epo) Patents (Class 257/E29.129)
  • Patent number: 10892264
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10038069
    Abstract: A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 31, 2018
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim
  • Patent number: 9625381
    Abstract: Provided is a sensor having a nanostructure as a sensing element and a fabrication method thereof. The sensor includes a nanostructure as a sensing element for sensing a marker over a substrate, wherein the nanostructure includes: a linker layer, including linkers, bonded to the substrate; and metallic nanoparticles grown from metal ions bonded to the linkers.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 18, 2017
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim
  • Patent number: 9437751
    Abstract: A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: September 6, 2016
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim
  • Patent number: 9040375
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 9029931
    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba
  • Patent number: 8987802
    Abstract: A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Donovan Lee, James Kai, Vinod Purayath, George Matamis, Steven J. Radigan
  • Patent number: 8987801
    Abstract: Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8969940
    Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (211, 213), charge storage layers (219), inlaid control gates (223, 224), and inlaid control gate contact regions (228).
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jane A Yater, Cheong Min Hong, Sung-Taeg Kang, Asanga H Perera
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8921923
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of charge storage layers each including a lower portion and an upper portion provided on the lower portion and having a smaller width than the lower portion, and a plurality of sacrificial films provided between the upper portions of adjacent ones of the charge storage layers. The sacrificial films are projected higher than the upper portions and spaced by first gaps from sidewalls of the upper portions. The method includes forming a plurality of intermediate insulating films on the upper portions and in the first gaps. The method includes removing the sacrificial films and forming second gaps between adjacent ones of the intermediate insulating films. The method includes forming a control electrode on the intermediate insulating films and in the second gaps.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Sasaki
  • Patent number: 8921915
    Abstract: A nonvolatile memory device includes a multi-finger type control gate formed over a substrate, a multi-finger type floating gate formed over the substrate and disposed close to the control gate with gaps defined therebetween, and spacers formed on sidewalls of the control gate and the floating gate, and filling the gaps.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung-Kun Park
  • Patent number: 8921912
    Abstract: A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Nam-Jae Lee, Seiichi Aritome
  • Patent number: 8912589
    Abstract: Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 16, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Hongmei Wang
  • Patent number: 8896049
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped stacked bodies; forming an insulating film to cover the plurality of island-shaped stacked bodies; removing a part of the insulating film to expose a surface of the first conductive film, such that a surface of the first conductive film almost coextensive with a height of the insulating film; forming a second conductive film over the first conductive film and a left part of the insulating film; forming a resist over the second conductive film; selectively removing the first conductive film and the second conductive film using the resist as a mask.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Tamae Takano, Yasuyuki Arai, Fumiko Terasawa
  • Patent number: 8896048
    Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Richard Fastow, Zhigang Wang, Yue-Song He, Kazuhiro Mizutani, Pavel Fastenko
  • Patent number: 8890232
    Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Shiuan Tsair, Wen-Ting Chu, Po-Wei Liu, Wen-Tuo Huang, Yu-Hsiang Yang, Chieh-Fei Chiu, Yu-Ling Hsu
  • Patent number: 8890231
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8890229
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; and a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body. The stacked body includes a plurality of staircase regions. The each of the plurality of electrode layers includes an exposed portion. The exposed portion is not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers. And the exposed portion of each of the plurality of electrode layers is disposed in one of the plurality of staircase regions.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Watanabe
  • Patent number: 8872239
    Abstract: An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuaki Tashiro, Shin Kikuchi
  • Patent number: 8872251
    Abstract: An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8859364
    Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 14, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shaw-Hung Ku, Chi-Pei Lu, Chun-Lien Su
  • Patent number: 8816421
    Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Neal Kistler
  • Patent number: 8809932
    Abstract: In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Kyu Cho, Se-Hoon Lee, Kyu-Charn Park, Choong-Ho Lee
  • Patent number: 8809934
    Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.
    Type: Grant
    Filed: August 4, 2013
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Yasushi Ishii
  • Patent number: 8786006
    Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8785268
    Abstract: A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Lei Xue, Kuo-Tung Chang
  • Patent number: 8759898
    Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics S.A.
    Inventor: Pascal Fornara
  • Patent number: 8748964
    Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Rhett T. Brewer, Durai V. Ramaswamy
  • Patent number: 8735959
    Abstract: A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: Erwan Dornel
  • Patent number: 8722490
    Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Giorgio Servalli, Daniela Brazzelli
  • Patent number: 8704289
    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a gate insulating film, a floating gate, first and second silicon oxide films, an insulating film and a control gate. The floating gate is formed on the gate insulating film. The first silicon oxide film is formed on an upper surface of the floating gate. The insulating film is formed on the first silicon oxide film on the upper surface of the floating gate and has a dielectric constant higher than that of the silicon oxide film. The second silicon oxide film is formed on the insulating film on the upper surface of the floating gate and on a side surface of the floating gate. The control gate is formed on the second silicon oxide film formed on the upper and side surfaces of the floating gate.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiro Shimura
  • Patent number: 8698223
    Abstract: A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 8685813
    Abstract: Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8686488
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Kondo, Nobutoshi Aoki, Takashi Izumida, Tomomi Yoda
  • Patent number: 8674414
    Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Jinho Kim, Kihyun Kim
  • Patent number: 8669607
    Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Shiuan Tsair, Wen-Ting Chu, Po-Wei Liu, Wen-Tuo Huang, Yu-Hsiang Yang, Chieh-Fei Chiu, Yu-Ling Hsu
  • Patent number: 8664711
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
  • Patent number: 8664710
    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 4, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shaw-Hung Ku, Chi-Pei Lu, Chun-Lien Su
  • Patent number: 8664708
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
  • Patent number: 8664712
    Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8659067
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 25, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
  • Patent number: 8653578
    Abstract: A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Jungal Choi
  • Patent number: 8643077
    Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyung Kim, Sung-Il Chang, Chang-Seok Kang, Jung-Dal Choi
  • Patent number: 8637914
    Abstract: Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 8629491
    Abstract: A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 14, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae Wook Yang
  • Patent number: 8614473
    Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: December 24, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Todd Abbott
  • Patent number: 8614474
    Abstract: The area C1 of the channel region of the drive TFT and the area C2 of the channel region of the memory TFT are set to have a relationship C1<C2 to an extent that allows predetermined hysteresis natures dependent on respective functions thereof.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 24, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Tomida
  • Patent number: 8587036
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 19, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shih-Chen Wang, Wen-Hao Ching