Gate Electrodes For Transistors With Floating Gate (epo) Patents (Class 257/E29.129)
  • Patent number: 6653188
    Abstract: The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: November 25, 2003
    Assignee: Nanya Technology Corp.
    Inventors: Yung-Meng Huang, Chi-Hei Lin, Ching-Nan Hsiao