Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.

Abstract: Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.

Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.

Abstract: In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.

Abstract: Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected only to second portions of second word lines of the memory device, where each first word line is adjacent at least one second word line. One or more contacts can be used to connect a conductive strap to its respective word line.

Abstract: There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memory cells sharing a source, and disposed at symmetrical positions, respectively, and two lengths of metal interconnections (the bit lines) are disposed with respect to a width in the direction of a channel width of a region occupied by one of the memory cells. In contrast, respective control gates of the memory cells corresponding to two word are rendered at an identical potential, and respective memory gates thereof are rendered at an identical potential, thereby disposing three lengths of metal interconnections (a control gate control line, memory gate control line, and common source line) with respect to a length of the regions occupied by the two memory cells in the direction of a channel length.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: A one time programmable memory including a first memory cell is provided. The first memory cell is disposed on a substrate having a trench disposed therein. The first memory cell includes a floating gate, a select gate, a first doped region, a second doped region and a third doped region. The floating gate is disposed on the sidewall of the trench. The select gate is disposed on the substrate outside the trench. The first doped region is disposed in the substrate at the bottom of the trench. The second and third doped regions are disposed in the substrate on both sides of the trench, and the second doped region is disposed between the floating gate and the select gate.

Abstract: A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

Abstract: A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of the first gate (14) to face each other, and a second gate (16), the second gate (16) being a side gate provided at a side of the first gate (14) other than the side where the source (10) and the drain (12) are provided. This makes it possible to provide the semiconductor device in which a desired circuit characteristic is obtainable in a non-destructive manner and in a non-volatile fashion while reducing the trial production times thereof for IC development.

Abstract: A semiconductor integrated circuit device comprises an insulated-gate field-effect transistor, the insulated-gate field-effect transistor comprising a device isolation insulating film that is provided to extend from an inside of a semiconductor substrate and to project from an upper surface of the semiconductor substrate, and defines a device region on the semiconductor substrate, a gate insulation film that is provided on the device region, a gate electrode that is provided on the gate insulation film, source/drain regions that are provided in the semiconductor substrate on both sides of the gate electrode, an insulation layer that is provided on the gate electrode, and a contact line that penetrates the insulation layer and is put in contact with the gate electrode.

Abstract: A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer. Gate side-wall insulation films are formed on both side surfaces of the stacked-gate structure. The thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side. The width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the first intermediate structure comprising a floating gate layer disposed outwardly from the first dielectric layer, a second dielectric layer disposed outwardly from the floating gate layer, and a first polysilicon layer disposed outwardly from the second dielectric layer; (3) removing regions of the first intermediate structure to form at least one gate stack disposed outwardly from the first dielectric layer; and (4) forming at least one dielectric isolation region after the formation of the gate stacks, wherein the at least one dielectric isolation region is disposed between two gate stacks.

Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.

Abstract: An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

Abstract: A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned and the polysilicon layer is partially etched. Then, a sidewall spacer is formed on sidewalls of the partially etched polysilicon layer and the patterned mask layer. The partially etched polysilicon layer is then fully etched, maintaining a partially etched shape at its top edge due to the sidewall spacer. The mask layer and the sidewall spacer are removed, to form a floating gate having a near-round edge shape. After full etching, the polysilicon layer may be heat-treated such that its top edge shape may become more rounded, fluent and/or stress- and/or strain-relieving.

Abstract: Disclosed is a flash memory device with an enlarged control gate structure, and various methods of make same. In one illustrative embodiment, the device includes a plurality of floating gate structures formed above a semiconducting substrate, an isolation structure positioned between each of the plurality of floating gate structures and a control gate structure comprising a plurality of enlarged end portions, each of the enlarged end portions being positioned between adjacent floating gate structures.

Abstract: A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturbance-preventing insulating film formed in the bulk silicon substrate between a source region and a drain region of the device. According to selected embodiments of the invention, the disturbance-preventing insulating film is formed using a Shallow Trench Isolation (STI) forming process.

Abstract: A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pillar. A drain region of the second conductivity type is formed in an upper region of the pillar. A gate dielectric and conductor are arranged along a first side of the pillar. A capacitor dielectric and body capacitor plate are arranged along an opposite, second side of the pillar. A depletion region around the source region defines a floating body region within the pillar which forms both a body of an access transistor structure and a plate of a capacitor structure. The cell also provides gain with respect to charge stored within the floating body.

Abstract: The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very narrow. A channel region of a memory transistor is divided into two regions of a writing control region and a writing region. The writing control region and the writing region have different threshold voltages. Writing is only carried out in the writing region. The writing control region turns off when the amount of electric charges accumulated in a floating gate reaches a specific value due to writing. The writing control region is used as a switch for a writing operation to automatically stop writing. Accordingly, an involatile memory comprising a memory transistor, in which writing can be carried out at a high speed with low consumption power and which is superior in controlling a threshold voltage after writing or erasing, can be obtained.

Abstract: Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Accordingly, the interfacial properties of the polysilicon film can be improved. It is thus possible to improve an operating characteristic of a device by prohibiting concentration of an electric field at the portion.

Abstract: A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on the gate insulating film. The nonvolatile semiconductor memory device also includes electric charge storage insulating films formed on side surfaces of the control gate, memory gates formed on side surfaces of the sidewall insulating films to be higher than the sidewall insulating film, and a silicide film formed to connect the memory gates and the control electrode.

Abstract: In one embodiment, a semiconductor device comprises an insulated floating gate disposed on a semiconductor substrate, an insulated program gate formed at least on a side surface of the floating gate, and an insulated erase gate disposed adjacent the floating gate.

Abstract: Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.

Abstract: A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a thickness of a floating gate is over 1500 ?, problems in short process time and short mass production margin in an existing process can be solved while completely stripping a dielectric layer fence.

Abstract: A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces of the fin body. A floating gate electrode is formed on the inner dielectric layer pattern. The floating gate electrode has an uneven upper surface. An outer dielectric layer is formed on the floating gate electrode. A control gate electrode is formed on the outer dielectric layer.

Abstract: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A semiconductor device having reduced pitting may be formed from isolation layer patterns on a semiconductor substrate defining an active region, a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches.

Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

Abstract: A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturbance-preventing insulating film formed in the bulk silicon substrate between a source region and a drain region of the device. According to selected embodiments of the invention, the disturbance-preventing insulating film is formed using a Shallow Trench Isolation (STI) forming process.

Abstract: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.

Abstract: Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.

Abstract: The method of forming a floating gate array of a flash memory device includes: (a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined by device isolation films; (b) patterning the first nitride film to form a first nitride film pattern; (c) forming first oxide film spacers on sidewalls of the first nitride film pattern; (d) selectively removing the first nitride film pattern; (e) forming a plurality of second nitride film patterns separated by the first oxide film spacers on the capping oxide film; (f) selectively removing the first oxide film spacers interposed between the plurality of second nitride film patterns and a portion of the capping oxide film to expose a surface of the floating gate forming film between the second nitride film patterns; (g) forming a plurality of floating gate patterns by removing a portion of the floating gate forming film exposed using the second n

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer. The second polysilicon layer and the first polysilicon layer are patterned to form the floating gate.

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

Abstract: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.

Abstract: An aspect of the present invention provides a semiconductor device that includes a logic circuit including at least one transistor with a first channel type, a first transistor with a second channel type configured to provide the logic circuit with a first voltage at a specified timing, and a precharge control unit configured to turn on at least one first channel type transistor in the logic circuit during the time when the first transistor with the second channel type provides the logic circuit with the first voltage, the precharge control unit configured to precharge a node coupled to a transistor of the first channel type in the logic circuit.

Abstract: There are provided a method of fabricating a flash memory device and a flash memory device fabricated thereby. The method of fabricating a flash memory device includes forming an isolation layer defining an active region in a semiconductor substrate, wherein the isolation layer is formed to have a protrusion being higher than a top surface of the active region, and to provide a groove in the active region. A conductive layer pattern is formed in the groove. A buffer layer is formed on the semiconductor substrate having the conductive layer pattern. Then, an oxidation barrier layer pattern having a line shape opening across the active region is formed on the buffer layer. The buffer layer and an upper portion of the conductive layer pattern, which are exposed by the opening, are selectively oxidized to form a mask oxide layer at a cross region of the opening and the active region, and simultaneously to form a buffer oxide layer on the isolation layer adjacent to the mask oxide layer.

Abstract: Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.

Abstract: A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, and forming an insulating layer on a sidewall of the first gate. The method also includes forming a dummy spacer over the sidewall of the first gate, the first gate including the cap layer and the insulating layer, and removing the dielectric layer failing to be covered with the dummy spacer and the dummy spacer to form an exposed portion of the substrate. The method further includes forming a gate insulating layer on the exposed portion of the substrate, and forming a second gate overlapping one side of the first gate, wherein a split gate is configured with the first and second gates.

Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.

Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.