Lateral Transistor (epo) Patents (Class 257/E29.187)
  • Patent number: 8981477
    Abstract: A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8969961
    Abstract: A semiconductor body (10) comprises a field-effect transistor (11). The field-effect transistor (11) comprises a drain region (12) of a first conduction type, a source region (13) of the first conduction type, a drift region (16) and a channel region (14) of a second conduction type which is opposite to the first conduction type. The drift region (16) comprises at least two stripes (15, 32) of the first conduction type which extend from the drain region (12) in a direction towards the source region (13). The channel region (14) is arranged between the drift region (16) and the source region (13).
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 3, 2015
    Assignee: AMS AG
    Inventors: Jong Mun Park, Verena Vescoli, Rainer Minixhofer
  • Patent number: 8962436
    Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Ghavam G. Shahidi, Jeng-Bang Yau
  • Patent number: 8957475
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8946861
    Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8946862
    Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8946041
    Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8916952
    Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
  • Patent number: 8907453
    Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 9, 2014
    Assignee: Shanghai Hua Nec Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Xue, Jia Pan, Hao Li, Ying Cai, Xi Chen
  • Patent number: 8896021
    Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
  • Patent number: 8816389
    Abstract: An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 26, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Edward Coyne
  • Patent number: 8803193
    Abstract: An overvoltage protection device in combination with a filter, the overvoltage protection device having a first node for connection to a node to be protected, a second node for connection to a discharge node; and a control node; and wherein the filter comprises at least one of: (a) a capacitor connected between the first node and the discharge node; (b) a capacitor connected between the control node and the discharge node; or (c) an inductor in series connection with the first node.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 12, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Edward Coyne
  • Patent number: 8785969
    Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Episil Technologies Inc.
    Inventors: Chung-Yeh Lee, Pei-Hsun Wu, Shiang-Wen Huang
  • Patent number: 8786016
    Abstract: A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-June Jang
  • Patent number: 8779555
    Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
  • Patent number: 8669640
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8598625
    Abstract: An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Jam-Wem Lee, Yi-Feng Chang
  • Publication number: 20130299944
    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Yao Lai, Shyh-Wei Wang, Yen-Ming Chen
  • Patent number: 8546908
    Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: October 1, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dragan Zupac, Brian D. Griesbach, Theresa M. Keller, Joel M. Keys, Sandra J. Wipf, Evan F. Yu
  • Patent number: 8525261
    Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Shyi-Yuan Wu, Wing Chor Chan, Chien-Wen Chu
  • Patent number: 8502344
    Abstract: A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape first isolation trench surrounds the emitter electrode. A second isolation trench surrounds the first isolation trench. The region between the first isolation trench and the second isolation trench is an n-type isolation silicon region. The isolation silicon region is at the same potential as the emitter electrode. In the cross-sectional configuration traversing the gate electrode, the depth of the p base region in an interval corresponding to an arc-shape portion of the gate electrode is shallower than the depth of the p base region in an interval corresponding to a straight-line portion of the gate electrode.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 6, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hong-fei Lu
  • Publication number: 20130119516
    Abstract: Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 8431450
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Publication number: 20130075741
    Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.
    Inventors: Shekar Mallikarjunaswamy, François Hébert
  • Patent number: 8405186
    Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Mattias E. Dahlstrom, Peter B. Gray, David L. Harame, Russell T. Herrin, Alvin J. Joseph, Andreas D. Stricker
  • Patent number: 8324713
    Abstract: A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Chih-Ping Chao, Chih-Sheng Chang, Hua-Chou Tseng
  • Publication number: 20120286327
    Abstract: An overvoltage protection device in combination with a filter, the overvoltage protection device having a first node for connection to a node to be protected, a second node for connection to a discharge node; and a control node; and wherein the filter comprises at least one of: (a) a capacitor connected between the first node and the discharge node; (b) a capacitor connected between the control node and the discharge node; or (c) an inductor in series connection with the first node.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 15, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Edward Coyne
  • Publication number: 20120235280
    Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Tung HUANG, Chun-Tsung KUO, Shih-Chang LIU, Yeur-Luen TU
  • Patent number: 8217494
    Abstract: The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: July 10, 2012
    Assignee: Silicon Motion, Inc.
    Inventor: Te-Wei Chen
  • Publication number: 20120139009
    Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: International Business Machine Corporation
    Inventors: Tak H. Ning, Kevin K. Chan, Marwan H. Khater
  • Patent number: 8174070
    Abstract: A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20120104553
    Abstract: A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer.
    Type: Application
    Filed: October 12, 2011
    Publication date: May 3, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8129820
    Abstract: A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: March 6, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Hideo Yoshino, Hisashi Hasegawa
  • Publication number: 20120043643
    Abstract: An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.
    Type: Application
    Filed: March 7, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-ryul Chang, Oh-kyunm Kwon
  • Patent number: 8115247
    Abstract: A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the first diffusion layer, the plug coupled to the first diffusion layer; and a second diffusion layer formed on the semiconductor substrate at a position adjacent to the control gate.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takaaki Nagai
  • Patent number: 8115280
    Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Shuo-Mao Chen, Chin-Wei Kuo, Sally Liu
  • Patent number: 8093683
    Abstract: The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial layer, an emitter region (an N+ impurity layer) is formed on the front surface of the P impurity layer, and the epitaxial layer and an N+ impurity layer form a collector region. A connected portion of a base electrode and the base region (the P impurity layer) is located between the end of the base region (the P impurity layer) on a collector electrode side and the emitter region (the N+ impurity layer). It means that the electrodes for the collector, the base and the emitter are formed in this order. The base electrode and the emitter electrode are connected through a wiring (not shown). A P+ isolation layer for dividing the epitaxial layer into a plurality of island regions is further formed.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: January 10, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Tetsuo Shimamura
  • Patent number: 8022506
    Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: September 20, 2011
    Assignee: NXP B.V.
    Inventor: Adrianus W. Ludikhuize
  • Publication number: 20110198726
    Abstract: An N? layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N? layer, a trench isolation region is formed to surround the N? layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N? layer. Between trench isolation region and the N? layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N? layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Applicant: RENESAS ELECTRONIC CORPORATION
    Inventors: Tetsuya NITTA, Takayuki Igarashi
  • Patent number: 7982282
    Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dragan Zupac, Brian D. Griesbach, Theresa M. Keller, Joel M. Keys, Sandra J. Wipf, Evan F. Yu
  • Patent number: 7932580
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 26, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7932581
    Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: April 26, 2011
    Assignee: Mediatek Inc.
    Inventors: Ming-Tzong Yang, Ching-Chung Ko, Tung-Hsing Lee, Zheng Zeng
  • Patent number: 7932582
    Abstract: In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: April 26, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 7897995
    Abstract: A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 1, 2011
    Assignee: Mediatek Inc.
    Inventors: Ming-Tzong Yang, Tao Cheng, Ching-Chung Ko, Tung-Hsing Lee
  • Publication number: 20110012232
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20110012196
    Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region.
    Type: Application
    Filed: September 10, 2010
    Publication date: January 20, 2011
    Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 7868378
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 11, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Publication number: 20100252860
    Abstract: A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Inventors: Ming-Tzong Yang, Tao Cheng, Ching-Chung Ko, Tung-Hsing Lee
  • Publication number: 20100219504
    Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
    Type: Application
    Filed: March 1, 2010
    Publication date: September 2, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Shuo-Mao Chen, Chin-Wei Kuo, Sally Liu
  • Patent number: 7781835
    Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: August 24, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Bruce D. Marchant, Dean Probst