Lateral Transistor (epo) Patents (Class 257/E29.187)
  • Publication number: 20100163924
    Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Ta-Cheng Lin, Te-Chang Wu
  • Patent number: 7701038
    Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Chih-Ping Chao, Chih-Sheng Chang
  • Patent number: 7667295
    Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: February 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 7646060
    Abstract: Method for producing a field effect transistor having a source region (9), a drain region and a channel layer (11) interconnecting the source and drain regions, and including the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the edge of an implant, such as the source region (9), in the semiconductor material (1), where the edge (4c) of the sacrificial layer (4) is subsequently used to define the edge of a gate (16).
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: January 12, 2010
    Assignee: Cree Sweden AB
    Inventors: Christopher Harris, Andrei Konstantinov
  • Publication number: 20090243042
    Abstract: A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode; and an n type third semiconductor region provided between the first and second semiconductor regions. The third semiconductor region has a first layer and a second layer. The impurity concentration in the first layer is uniform. The second layer has a higher impurity concentration than the first layer that increases in a gradient from the first semiconductor region to the second semiconductor region.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 1, 2009
    Inventors: Kiyoharu HAYAKAWA, Masato TAKI
  • Publication number: 20090065899
    Abstract: The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial layer, an emitter region (an N+ impurity layer) is formed on the front surface of the P impurity layer, and the epitaxial layer and an N+ impurity layer form a collector region. A connected portion of a base electrode and the base region (the P impurity layer) is located between the end of the base region (the P impurity layer) on a collector electrode side and the emitter region (the N+ impurity layer). It means that the electrodes for the collector, the base and the emitter are formed in this order. The base electrode and the emitter electrode are connected through a wiring (not shown). A P+ isolation layer for dividing the epitaxial layer into a plurality of island regions is further formed.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 12, 2009
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Tetsuo SHIMAMURA
  • Publication number: 20090057773
    Abstract: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well; forming bases on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type and the n-type wells; and implanting n-type impurity ions into the p-type and the n-type wells through the second photosensitive layer pattern to form an emitter and a collector, respectively, to form the BJT. Therefore, CMOS manufacturing processes are used to form a high frequency BJT having improved frequency and noise characteristics.
    Type: Application
    Filed: August 20, 2008
    Publication date: March 5, 2009
    Inventor: Yeo-Jo Yun
  • Publication number: 20090026542
    Abstract: An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 29, 2009
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Uwe Wahl
  • Patent number: 7465964
    Abstract: A high voltage/power semiconductor device has a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. Low and high voltage terminals are connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region and a relatively highly doped injector region between the drift region and the high voltage terminal. The device has a relatively highly doped region in electrical contact with the highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 16, 2008
    Assignee: Cambridge Semiconductor Limited
    Inventor: Florin Udrea
  • Patent number: 7456469
    Abstract: The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an N-type polysilicon layer which contains of N-type impurities at an approximately constant concentration.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: November 25, 2008
    Assignee: Elpida Memory Inc.
    Inventor: Yasushi Yamazaki
  • Publication number: 20080283967
    Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 20, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroki Fujii
  • Patent number: 7446012
    Abstract: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P? collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 4, 2008
    Assignee: BCD Semiconductor Manufacturing Limited
    Inventors: Chong Ren, Xian-Feng Liu, Bin Qiu
  • Publication number: 20080150083
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 26, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Publication number: 20080122517
    Abstract: Semiconductor devices and methods are disclosed wherein a switching element or a current path is coupled to a substrate, and wherein a further element is coupled to said substrate and a control input of said switching element or said current path. Accordingly, in at least one embodiment, a semiconductor device comprises a substrate and a switching element with a control input coupled to the substrate. The semiconductor device includes a compensation element having a control input and an output. The control input of the compensation element is coupled to the substrate and the output of the compensation element is coupled to the control input of the switching element.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Applicant: Infineon Technologies AG
    Inventors: Joachim Pichler, Maria Giovanna Lagioia
  • Publication number: 20080061401
    Abstract: A bipolar-junction transistor is disclosed comprising a first layer, a second layer, and a third layer, the surfaces of the layers modified for more precise control of electron function. The surfaces are modified to have a periodically repeating structure of indents where the indentations are of dimensions so as to create de Broglie wave interference, leading to a change in electron work function.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 13, 2008
    Inventor: Isaiah Watas Cox
  • Patent number: 7332778
    Abstract: To refine a semiconductor device (100), in particular a S[ilicon]O[n]I[nsulator] device, comprising: at least one isolating layer (10) made of a dielectric material; at least one silicon substrate (20) arranged on said isolating layer (10); at least one component (30) integrated in the silicon substrate (20), which component has at least one slightly doped zone (34); as well as at least a first, in particular planar, metallization region (40) arranged between the isolating layer (10) and the component (30), in particular between the isolating layer (10) and the slightly doped zone (34) of the component (30), as well as a method of manufacturing at least one semiconductor device (100) in such a manner that trouble-free operation also of slightly doped components (30), such as pnp transistors, is guaranteed in a SOI process transferred onto the insulator, it is proposed that at least a second, in particular planar, metallization region (42) is arranged on the side of the silicon substrate (20) facing away fr
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: February 19, 2008
    Inventors: Wolfgang Schnitt, Hauke Pohlmann
  • Publication number: 20080023794
    Abstract: An integrated circuit including a bipolar transistor is disclosed. One embodiment provides an insulation structure used to form a junction insulation, a collector structure formed inside a semiconductor zone having openings dividing the collector structure into collector zones. The collector zones are arranged in such a manner that a shortest lateral distance between an emitter zone and the insulation structure runs at least through one of the collector zones.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 31, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Prechtl, Marcel Kreuzberg
  • Publication number: 20080023796
    Abstract: A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 31, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD., SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Keiji Mita, Yasuhiro Tamada, Kentaro Ooka
  • Patent number: 7309905
    Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: December 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Jiaw-Ren Shih, Fu Chin Yang
  • Patent number: 7247926
    Abstract: A high-frequency switching transistor comprises a collector area, which has a first conductivity type, a first barrier area bordering on the collector area, which has a second conductivity type which differs from the first conductivity type, and a semiconductor area bordering on the first barrier area, which has a dopant concentration which is lower than a dopant concentration of the first barrier area. Further, the high-frequency switching transistor has a second barrier area bordering on the semiconductor area, which has a first conductivity type, as well as a base area bordering on the second barrier area, which has a second conductivity type. Additionally, the high-frequency switching transistor comprises a third barrier area bordering on the semiconductor area, which has the second conductivity type and a higher dopant concentration than the semiconductor area. Further, the high-frequency switching transistor has an emitter area bordering on the third barrier area, which has the first conductivity type.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: July 24, 2007
    Assignee: Infineon Technologies AG
    Inventor: Reinhard Losehand
  • Patent number: 7238576
    Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Yamaguchi, Ichiro Omura, Wataru Saito, Takashi Shinohe, Hiromichi Ohashi
  • Patent number: 7187056
    Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: March 6, 2007
    Assignee: Intersil Americas, Inc.
    Inventors: Nicolaas W. van Vonno, Dustin Woodbury
  • Patent number: RE41477
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 10, 2010
    Inventor: James D. Beasom