Transistor With Vertical Current Flow (epo) Patents (Class 257/E29.198)
  • Patent number: 9041050
    Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Matsuura
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8994066
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8952553
    Abstract: The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: February 10, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaru Senoo, Tomohiko Sato
  • Patent number: 8946002
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 8933483
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Patent number: 8928031
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 6, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8866262
    Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Toru Hiyoshi
  • Patent number: 8866263
    Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Marie Denison
  • Patent number: 8860025
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans-Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8809911
    Abstract: Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 8809986
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 19, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Patent number: 8772827
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8742474
    Abstract: A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 3, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiaki Hisamoto, Atsushi Narazaki, Hitoshi Uemura
  • Patent number: 8735989
    Abstract: According to one embodiment, a semiconductor device includes a main element and a sense element. The main element is connected between a collector terminal and an emitter terminal. The main element has an insulated gate bipolar transistor structure. The sense element is connected in parallel with the main element via a sense resistor between the collector terminal and the emitter terminal. The sense element has an insulated gate bipolar transistor structure with a feedback capacitance larger than a feedback capacitance of the main element.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Matsushita
  • Patent number: 8729601
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 20, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20140118055
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 8680610
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 25, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20140070265
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • Patent number: 8643146
    Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Uemura
  • Publication number: 20140027813
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: Marian Kuruc, Iuraj Vavro
  • Publication number: 20130334565
    Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Patent number: 8598623
    Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8541834
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuro Nozu
  • Publication number: 20130234200
    Abstract: A method for manufacturing a vertical trench IGBT includes: forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming a trench passing through the body layer; forming a trench gate in the trench via a gate insulating film; forming a polysilicon film containing an impurity of a first conductivity type on the body layer; diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 12, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hidenori FUJII
  • Publication number: 20130187195
    Abstract: A cell field has an edge and a center, an individual device cells are connected in parallel. A first type of device cells has a body region with a first size and a source region with a second size implemented in the body region, and a second type of device cells has a body region of the first size and in which a source region is omitted or the source region is smaller than the second size. The cell field includes non-overlapping cell regions, each including the same plurality of device cells. At least one sequence of cell regions is arranged between the edge and center of the cell field in which the frequency of device cells of the second type monotonically increases from cell region to cell region in the direction of the center, and one cell region of the sequence of cell regions includes or adjoins the center.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Hubert Rothleitner
  • Publication number: 20130168728
    Abstract: A lateral insulated-gate bipolar transistor includes a buried insulation layer which opens only part of the collector ion implantation region and isolates the other regions, thereby reducing the loss by the turn-off time. The lateral insulated-gate bipolar transistor further includes a deep ion implantation region formed to face towards the open part of the collector ion implantation region, thereby decreasing the hole current injected into a base region under an emitter ion implantation region, and thereby greatly increasing the latch-up current level by relatively increasing the hole current injected into the deep ion implantation region having no latch-up effect.
    Type: Application
    Filed: May 3, 2012
    Publication date: July 4, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Sang Yong LEE
  • Publication number: 20130105856
    Abstract: A semiconductor device includes a semiconductor substrate which functions as an n? drift layer, a trench IGBT formed in the front surface, an interlayer insulator film, and a metal electrode layer on the interlayer insulator film. There is a contact hole in the interlayer insulating film which has a first opening formed on the metal electrode layer side and a second opening on the semiconductor substrate side. Width w1 of the first opening on the metal electrode layer side is wider than width w2 of first opening on the semiconductor substrate side, in a direction perpendicular to the extending direction of the trench in the planar pattern of trenches. The metal electrode layer is connected to a p-type channel region and an n+ source region via the contact hole. The method of manufacturing improves the reliability of the device.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: FUJI ELECTRIC CO., LTD.
  • Patent number: 8426944
    Abstract: In some embodiments, an insulated gate bipolar transistor includes a drift layer, insulation gates formed at a principle surface portion of the drift layer, base regions formed in a between-gate region, an emitter region formed in the base region so as to be adjacent to the insulation gate, an emitter electrode connected to the emitter region, a collector layer formed at the other side of the principle surface portion of the drift layer, and a collector electrode connected to the collector layer. The conductive type base regions are separated with each other by the drift layers, and the drift layer and the emitter electrode are insulated by an interlayer insulation film.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 23, 2013
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Shuji Yoneda, Kenji Sawamura
  • Patent number: 8421184
    Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer and a second semiconductor layer formed on a first surface; a diode having a first electrode and a second electrode; a control pad; a control electrode electrically coupled with the control pad; and an insulation member. The first electrode is formed on a second surface of the first semiconductor layer. The second electrode is formed on the first surface. Current flows between the first electrode and the second electrode. The control pad is arranged on the first surface so that the pad inputs a control signal for controlling an injection amount of a carrier into the first semiconductor layer. The insulation member insulates between the control electrode and the second electrode and between the control electrode and the semiconductor substrate.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: April 16, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yoshiko Fukuda, Yuji Fukuda, Mika Ootsuki
  • Publication number: 20130075783
    Abstract: A semiconductor device includes: a semiconductor substrate, the semiconductor substrate comprising; an n type drift layer, a p type body layer on an upper surface side of the drift layer, and a high impurity n layer on a lower surface side of the drift layer. The high impurity n layer includes hydrogen ion donors as a dopant, and has a higher density of n type impurities than the drift layer. A lifetime control region including crystal defects as a lifetime killer is formed in the high impurity n layer and a part of the drift layer. A donor peak position is adjacent or identical to a defect peak position, at which a crystal defect density is highest in the lifetime control region in the depth direction of the semiconductor substrate. The crystal defect density in the defect peak position of the lifetime control region is 1×1012 atoms/cm3 or more.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya YAMAZAKI, Satoru KAMEYAMA, Hitoshi SAKANE, Jyoji ITO
  • Publication number: 20130069109
    Abstract: According to an embodiment, a trench structure and a second semiconductor layer are provided in a semiconductor device. In the trench structure, a trench is provided in a surface of a device termination portion with a first semiconductor layer of a first conductive type including a device portion and the device termination portion, and an insulator is buried in the trench in such a manner to cover the trench. The second semiconductor layer, which is of a second conductive type, is provided on the surface of the first semiconductor layer, is in contact with at least a side on the device portion of the trench, and has a smaller depth than the trench. The insulator and a top passivation film for the semiconductor device are made of the same material.
    Type: Application
    Filed: March 13, 2012
    Publication date: March 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shizue MATSUDA, Shingo SATO, Wataru SAITO
  • Patent number: 8399907
    Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 19, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee
  • Publication number: 20130056731
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Publication number: 20130056790
    Abstract: According to one embodiment, a semiconductor device includes: a drain layer; a drift layer formed on the drain layer, an effective impurity concentration of the drift layer being lower than an effective impurity concentration of the drain layer; a base layer formed on the drift layer; a source layer selectively formed on the base layer; a gate insulating film formed on inner surfaces of trenches, the trenches piercing the base layer from an upper surface of the source layer; a gate electrode filled into an interior of the trench; an inter-layer insulating film formed on the trench to cover an upper surface of the gate electrode, at least an upper surface of the inter-layer insulating film being positioned higher than the upper surface of the source layer; and a contact mask. The contact mask is formed on the inter-layer insulating film, and is conductive or insulative.
    Type: Application
    Filed: March 19, 2012
    Publication date: March 7, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Keiko KAWAMURA
  • Patent number: 8384194
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 26, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130037852
    Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.
    Type: Application
    Filed: July 13, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro TAMAKI
  • Publication number: 20130037853
    Abstract: A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.
    Type: Application
    Filed: February 18, 2011
    Publication date: February 14, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Publication number: 20130026536
    Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Donato Corona, Giovanni Sammatrice, Sebastiano Amara, Salvatore Pisano, Antonio Giuseppe Grimaldi
  • Publication number: 20130015493
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Application
    Filed: May 24, 2012
    Publication date: January 17, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru SENOO
  • Publication number: 20130015494
    Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
    Type: Application
    Filed: September 21, 2012
    Publication date: January 17, 2013
    Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.
    Inventor: ALPHA & OMEGA SEMICONDUCTOR, INC.
  • Publication number: 20130001640
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Publication number: 20120326207
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 27, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Publication number: 20120319189
    Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee, Wen-Fang Lee
  • Patent number: 8334565
    Abstract: A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n+-type emitter region and a p+-type body region formed thereon, and the surfaces of regions are alternately arranged along the trench in the longitudinal direction thereof with an emitter electrode being in common contact with both of the surfaces of the n+-type emitter region and the p+-type body region. A plurality of second inter-trench surface regions are provided each of which is formed along the trench in the longitudinal direction thereof with one of the surface of the p base region and the surface of the n-type semiconductor substrate.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: December 18, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Publication number: 20120292662
    Abstract: The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 22, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hitoshi MATSUURA, Yoshito NAKAZAWA
  • Publication number: 20120286324
    Abstract: Provided is a manufacturing method for an insulated-gate bipolar transistor (IGBT). The manufacturing method includes providing a structure including a substrate, a first conductivity type epitaxial layer formed on the substrate, a gate electrode formed on a first surface of the epitaxial layer, a second conductivity type body region formed at opposite sides of the gate electrode in the first surface of the epitaxial layer, and a first conductivity type source region formed within the body region; removing a portion of the substrate by back grinding; and removing the other portion of the substrate by etching until the second surface of the epitaxial layer is exposed.
    Type: Application
    Filed: April 5, 2012
    Publication date: November 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Nam-Young Lee
  • Patent number: 8299494
    Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: October 30, 2012
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20120261714
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo Oosawa
  • Publication number: 20120261677
    Abstract: Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.
    Type: Application
    Filed: June 25, 2012
    Publication date: October 18, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki KAWADA, Takeshi TAWARA