And Gate Structure Lying On Slanted Or Vertical Surface Or Formed In Groove (e.g., Trench Gate Igbt) (epo) Patents (Class 257/E29.201)
  • Patent number: 10038052
    Abstract: A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift region doped with a first dopant type, an edge termination region (ER) laterally surrounding the active area (AA), a channelstopper terminal provided at the front surface and located in the edge termination region (ER), and a first suppression trench located on a side of the channelstopper terminal towards the active region (AA), and provided adjacent to the channelstopper terminal. Further, a production method for such a semiconductor device is provided.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Frank Dieter Pfirsch, Hans-Joachim Schulze, Stephan Voss
  • Patent number: 9443958
    Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ming-Shun Hsu
  • Patent number: 9006063
    Abstract: A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 ?m.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Yean Ching Yong, Stefania Fortuna
  • Patent number: 9000479
    Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8940604
    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Patent number: 8928071
    Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8907411
    Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Chi-Sheng Peng
  • Patent number: 8884365
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8872260
    Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Jung-Yi Guo, Chun-Min Cheng
  • Patent number: 8847233
    Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 8847307
    Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 30, 2014
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 8841722
    Abstract: A semiconductor device includes a semiconductor substrate having a first groove. The first groove has a bottom and first and second side surfaces opposite to each other. A first gate insulator extends alongside the first side surface. A first gate electrode is formed in the first groove and on the first gate insulator. A second gate insulator extends alongside the second side surface. A second gate electrode is formed in the first groove and on the second gate insulator. The second gate electrode is separate from the first gate electrode.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Masayoshi Sammi
  • Patent number: 8835254
    Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 16, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yoshiaki Toyoda, Takatoshi Ooe
  • Patent number: 8829609
    Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Donato Corona, Giovanni Samma Trice, Sebastiano Amara, Salvatore Pisano, Antonio Giuseppe Grimaldi
  • Patent number: 8829604
    Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeharu Okaji
  • Patent number: 8809944
    Abstract: A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Kawaguchi
  • Patent number: 8809945
    Abstract: A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 ?m or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×1017 cm?3 or greater.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 19, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8809911
    Abstract: Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 8779507
    Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takuji Miyata, Kazumasa Takenaka
  • Patent number: 8766317
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device, if an embedded electrode is at negative potential, a depletion layer is formed from a trench to a neighboring trench so that a channel is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: July 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8759911
    Abstract: Plural island-form emitter cells (22) having a p-base region (23) and an n+ emitter region (24) are provided, distanced from each other, on a main surface of an n? layer (21). A trench (25) deeper than the p-base region (23) is formed on either side of the emitter cell (22). A first gate electrode (26) is embedded in the trench (25) across a first gate insulating film (41). A second gate electrode (27) that electrically connects first gate electrodes (26) is provided, across a second gate insulating film (40), on a surface of a region of the p-base region (23) sandwiched by the n+ emitter region (24). A conductive region (28) that electrically connects second gate electrodes (27) is provided, across a third gate insulating film (42), on a surface of the n? layer (21). A contact region (29) that is isolated from the second gate electrode (27), and that short circuits the n+ emitter region (24) and p-base region (23), is provided.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 24, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hong-fei Lu
  • Patent number: 8754473
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: June 17, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8748979
    Abstract: Disclosed is a semiconductor device whose breakdown voltage is made high by controlling local concentration of an electric field. A source region faces a second plane, one of side faces of a groove part, and a part thereof extends in a direction in parallel to a nodal line of first and second planes. A drift region faces a third plane being the other side face of the groove part opposite to the second plane with a part thereof extending in a direction parallel to the nodal line of the first plane and the third plane, and is formed at a lower concentration than the source region. The drain region is provided so as to be placed on the other side of the drift region opposite to the groove part and so as to touch the drift region, and is formed at a higher concentration than the drift region.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Takeda
  • Patent number: 8728881
    Abstract: Semiconductor devices and methods for manufacturing the semiconductor devices are disclosed. A semiconductor device includes a substrate, a fin formed above the substrate with a semiconductor layer formed between the substrate and the fin, and a gate stack crossing over the fin. The fin and the semiconductor layer may include different materials and have etching selectivity with respect to each other. A patterning of the fin can be stopped reliably on the semiconductor layer. Therefore, it is possible to better control the height of the fin and thus the channel width of the final device.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: May 20, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Patent number: 8723220
    Abstract: A reverse conducting semiconductor device having an IGBT element region and a diode element region in one semiconductor substrate is provided. An electric current detection region is arranged adjacent to the IGBT element region, and a collector region of the IGBT element region is extended to connect with a collector region of the electric current detection region. Instability in the IGBT detection current caused by a boundary portion between the IGBT and the diode can be suppressed. In the same way, an electric current detection region is arranged adjacent to the diode element region, and a cathode region of the diode element region is extended to connect with a cathode region of the electric current detection region. Instability in the diode detection current caused by the boundary portion between the IGBT and the diode can be suppressed.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 13, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Akitaka Soeno
  • Patent number: 8710510
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 8710542
    Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Tosiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8704302
    Abstract: The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: April 22, 2014
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Amit Paul, Mohamed N. Darwish
  • Patent number: 8698195
    Abstract: A stabilizing plate portion is formed in a region of a first main surface lying between first and second insulated gate field effect transistor portions. The stabilizing plate portion includes a first stabilizing plate arranged closest to the first insulated gate field effect transistor portion and a second stabilizing plate arranged closest to the second insulated gate field effect transistor portion. An emitter electrode is electrically connected to an emitter region of each of the first and second insulated gate field effect transistor portions, electrically connected to each of the first and second stabilizing plates, and arranged on the entire first main surface lying between the first and second stabilizing plates, with an insulating layer being interposed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Oya, Katsumi Nakamura
  • Patent number: 8680610
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 25, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8680609
    Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: March 25, 2014
    Assignee: Sinopower Semiconductor Inc.
    Inventors: Wei-Chieh Lin, Jia-Fu Lin
  • Patent number: 8653606
    Abstract: It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 18, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Masaki Shiraishi
  • Patent number: 8643090
    Abstract: In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
  • Patent number: 8643102
    Abstract: A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Masahiro Masunaga
  • Patent number: 8643103
    Abstract: A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiya Kawashima
  • Publication number: 20140027812
    Abstract: A semiconductor device includes a trench extending into a drift zone of a semiconductor body from a first surface. The semiconductor device further includes a gate electrode in the trench and a body region adjoining a sidewall of the trench. The semiconductor device further includes a dielectric structure in the trench. The dielectric structure includes a high-k dielectric in a lower part of the trench. The high-k dielectric includes a dielectric constant higher than that of SiO2. An extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Hans-Peter Felsl, Franz-Josef Niedernostheide
  • Patent number: 8633510
    Abstract: The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8633529
    Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8618604
    Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Atsushi Narazaki
  • Patent number: 8618601
    Abstract: A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 31, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: John Chen
  • Patent number: 8618600
    Abstract: Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 31, 2013
    Assignee: Qimonda AG
    Inventor: Stafan Slesazeck
  • Publication number: 20130341673
    Abstract: A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body. The first and second emitter regions are arranged between the drift region and a first electrode and are each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source region and the body region. A floating parasitic region of the first conductivity type is disposed outside the cell region.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 8610205
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Dean E. Probst
  • Patent number: 8610235
    Abstract: A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
  • Patent number: 8587047
    Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Wei Ting, Shing-Hwa Renn, Yu-Teh Chiang, Chung-Ren Li, Tieh-Chiang Wu
  • Patent number: 8580667
    Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 12, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 8541836
    Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
  • Patent number: 8541834
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuro Nozu