Abstract: A collector region is not formed in at least a portion of an ineffective region where an insulating film is formed on a front face of an IGBT. In this portion in which the collector region is not formed, a collector electrode and a buffer layer contact each other. Since the buffer layer and the collector region differ from each other in conductivity type, no electric charge is introduced from the collector electrode into the buffer layer. Thus, introduction of electric charges into a drift region at a portion in the ineffective region is suppressed, which alleviates electric field concentration in a semiconductor substrate. Further, in the IGBT, the semiconductor substrate and the collector electrode contact each other and heat transfer to the collector electrode is not hindered even in the range where the collector region is not formed. Thus, concentration of heat generation in the semiconductor substrate is alleviated.

Abstract: A protection device of programmable semiconductor surge suppressor having deep-well structure is provided comprising one, two or four protection units, each of which is composed of a PN-junction diode, a PNPN-type thyristor and a NPN-type triode connected with each other. It is characterized in that in the diode area on the frontal side of the N-type semiconductor base is formed a PN junction with impurity concentration changed gradiently from top to bottom according to the order of P+, P, N and N+; and a group of deep-wells with P-type impurities are positioned at the interface of the PN junction, making the PN junction form a concave-convex type interface. The present invention can be used in the program-controlled switchboard to protect the Subscriber Line Interface Circuit (SLIC) board. The above improvement can further improve the anti-lightning and anti-surge performance and the energy discharge capability of the whole device.

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit.

Abstract: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.

Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

Abstract: A protection device of programmable semiconductor surge suppressor having deep-well structure is provided comprising one, two or four protection units, each of which is composed of a PN-junction diode, a PNPN-type thyristor and a NPN-type triode connected with each other. It is characterized in that in the diode area on the frontal side of the N-type semiconductor base is formed a PN junction with impurity concentration changed gradiently from top to bottom according to the order of P+, P, N and N+; and a group of deep-wells with P-type impurities are positioned at the interface of the PN junction, making the PN junction form a concave-convex type interface. The present invention can be used in the program-controlled switchboard to protect the Subscriber Line Interface Circuit (SLIC) board. The above improvement can further improve the anti-lightning and anti-surge performance and the energy discharge capability of the whole device.

Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.

Abstract: Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and two cathodes connected to the protected circuit, the two diodes are formed in a well-in-well structure on the semiconductor substrate, and the well-in-well structure includes a P-type well forming the floating gate, an N-type well which surrounds the surfaces of the P-type well other than that on the front side of the substrate with the deep portion side of the substrate so as to form the cathode of one of the diodes, and a first N-type region formed in the P-type well so as to form the cathode of the other diode.

Abstract: Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells.

Abstract: A bipolar semiconductor device and manufacturing method. One embodiment provides a diode structure including a structured emitter coupled to a first metallization is provided. The structured emitter includes a first weakly doped semiconductor region of a first conductivity type which forms a pn-load junction with a weakly doped second semiconductor region of the diode structure. The structured emitter includes at least a highly doped first semiconductor island of the first conductivity type which at least partially surrounds a highly doped second semiconductor island of the second conductivity type.

Abstract: Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage.

Abstract: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.

Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: A semiconductor thyristor device includes a semiconductor substrate, two transistors each of which is different junction type from the other and which are provided adjacent to each other in the semiconductor substrate to constitute one thyristor element, a first wiring layer that is formed on the semiconductor substrate and provides a ground potential to one of the transistors, and a second wiring layer that is formed on the semiconductor substrate and provides a power source potential to the other of the transistors. The first wiring layer covers a region in the semiconductor substrate in which the two transistors adjoin each other. This avoids a leakage current that might be generated due to any potential of a wiring layer for another circuit in a chip layout.

Abstract: An electronic device including a protection circuit for a light-emitting device An electronic device is provided that includes a protection circuit for a light-emitting device. The protection circuit comprises a first node adapted to be coupled to an anode of the light-emitting device and a second node adapted to be coupled to a cathode of the light-emitting device. A voltage detection stage is coupled between the first and second nodes. The voltage detection stage is adapted to detect an overvoltage condition between the first and second nodes. Furthermore, the protection circuit comprises a thyristor coupled with its anode to the first node, its cathode to the second node to the voltage detection stage. When the overvoltage condition is detected in normal operation the thyristor is controlled to open so that the current can flow through the thyristor.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.

Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.

Abstract: A vertical thyristor adapted to an HF control, including a cathode region in a P-type base well, a lightly-doped P-type layer next to the base well, a lightly-doped N-type region in the lightly-doped P-type layer, a Schottky contact on the lightly-doped N-type region connected to a control terminal, and a connection between the lightly-doped N-type region and the P-type base well.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1—N2—P2—N1//N1—P3—N3—P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 ?m or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm?2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm?2.

Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

Abstract: A thyristor arrangement includes a main thyristor, at least one auxiliary thyristor, a resistance device which electrically connects the auxiliary thyristor and the main thyristor to one another, and an optical triggering device for breakover triggering of the main thyristor via the auxiliary thyristor and the resistance device. The resistance device defines a time-dependent ohmic resistance in such a way that the value thereof is relatively large during a switch-on phase of the main thyristor and relatively small during a current-carrying phase of the main thyristor.

Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping ,concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

Abstract: Disclosed herein is a semiconductor device including: an element forming region of a semiconductor substrate isolated by an element isolating region formed in the semiconductor substrate; an insulating film formed on the semiconductor substrate; an opening portion formed in the insulating film to include a region to be selectively epitaxially grown in the element forming region; and a semiconductor layer formed by selective epitaxial growth of the element forming region of the semiconductor substrate in the opening portion.

Abstract: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract: A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor switching device electrically coupled to the first metallized face of the wafer and having at least one electrode region; and an interconnect bonded to the semiconductor switching device. The interconnect includes a first metal layer bonded to the at least one electrode region of the semiconductor switching device, a ceramic layer bonded to the first metal layer, the ceramic layer defining a via for accessing the first metal layer, a second metal layer bonded to the ceramic layer, and a conducting substance disposed in the via of the ceramic layer to electrically couple the first metal layer to the second metal layer.

Abstract: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an epitaxial silicon layer (20) formed upon the anode (10) and the second gate electrode (14) is an epitaxial silicon-germanium layer (24) formed upon the first gate electrode (12). The method of fabricating such a vertical thyristor comprises the steps of depositing an epitaxial silicon layer (20) upon the anode (10) and depositing an epitaxial silicon-germanium layer (24) upon the epitaxial silicon layer (20), wherein the epitaxial silicon layer (20) forms the first gate electrode (12) and the epitaxial silicon-germanium layer (24) forms the second gate electrode (14) of the vertical thyristor.

Abstract: Two operation channels CH1 and CH2 of a bidirectional photothyristor chip 31 are disposed away from each other so as not to intersect with each other. In between a P-gate diffusion region 23 on the left-hand side and a P-gate diffusion region 23? on the right-hand side on an N-type silicon substrate, and in between the CH1 and the CH2, a channel isolation region 29 comprised of an oxygen doped semi-insulating polycrystalline silicon film 35a doped with phosphorus is formed. Consequently, a silicon interface state (Qss) in the vicinity of the channel isolation region 29 on the surface of the N-type silicon substrate increases, so that holes or minority carriers in the N-type silicon substrate are made to disappear in the region. This makes it possible to prevent such commutation failure that when a voltage of the inverted phase is applied to the CH2 side at the point of time when the CH1 is turned off, the CH2 is turned on without incidence of light, and this allows a commutation characteristic to be enhanced.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.

Abstract: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.

Abstract: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity type is formed in the first anode region. A first semiconductor region of the first conductivity type is formed in contact with the semiconductor substrate. A second semiconductor region of the second conductivity type is formed adjacent to the first semiconductor region and in contact with the cathode layer. An intermediate electrode is formed on the surfaces of the first semiconductor region and the contact region.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: An apparatus for switching microwave signals includes a plurality of input lines, a plurality of output lines; and a plurality of thyristors. Each thyristor has a lower conducting surface that is electrically connected to one of the input lines and an upper conducting surface that is electrically connected to one of the output lines. A selected thyristor transmits a microwave signal between a selected input line and a selected output line in an ON state and blocks the microwave signal between the selected input line and the selected output line in an OFF state.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.

Abstract: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the second-conductivity-type region, respectively, at both ends of the semiconductor layer; and a gate electrode that is coupled to the second-conductivity-type region or the first-conductivity-type region in an intermediate area of the semiconductor layer, the gate electrode being provided over a plurality of faces of a semiconductor layer portion serving as the second-conductivity-type region or the first-conductivity-type region in the intermediate area.

Abstract: A resurf region of a second conductivity type and a base region of a first conductivity type adjacent to each other are formed in surface portions of a semiconductor substrate of the first conductivity type. An emitter region of the second conductivity type is formed in the base region to be spaced from the resurf region. A gate insulating film is formed to cover a portion of the base region disposed between the emitter region and the resurf region, and a gate electrode is formed on the gate insulating film. A top semiconductor layer of the first conductivity type electrically connected to the base region is formed in a surface portion of the resurf region. A collector region of the first conductivity type is formed in a surface portion of the resurf region to be spaced from the top semiconductor layer. The collector region and the top semiconductor layer have substantially the same impurity concentration and are disposed at substantially the same depth.