Structure Comprising Mos Gate And At Least One Non-mos Gate (e.g., Jfet Or Mesfet Gate) (epo) Patents (Class 257/E29.265)
  • Patent number: 9041049
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 8742473
    Abstract: Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Min-Chul Park, Young-Jin Choi, Nam-Ho Jeon
  • Patent number: 8735950
    Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8716763
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: May 6, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan
  • Patent number: 8653589
    Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8524552
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 8502280
    Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 8455938
    Abstract: The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: June 4, 2013
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Patent number: 8441048
    Abstract: The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESFET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 14, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Joseph E. Ervin, Trevor John Thornton
  • Publication number: 20130099293
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Li-Fan Chen, Wing-Chor Chan
  • Patent number: 8362529
    Abstract: A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: January 29, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Wei-Chieh Lin, Guo-Liang Yang, Shian-Hau Liao
  • Patent number: 8354698
    Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 15, 2013
    Assignee: System General Corp.
    Inventors: Hsin-Chih Chiang, Han-Chung Tai
  • Patent number: 8283715
    Abstract: An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: October 9, 2012
    Assignee: Rexchip Electronics Corporation
    Inventors: Yung-Chang Lin, Sheng-Chang Liang
  • Patent number: 8269263
    Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: September 18, 2012
    Assignee: Vishay-Siliconix
    Inventors: Jian Li, King Owyang
  • Patent number: 8258555
    Abstract: A semiconductor device includes a semiconductor substrate having a conductive type, a source metal layer, a gate metal layer, at least one transistor device, a heavily doped region having the conductive type, a capacitor dielectric layer, a conductive layer. The source metal layer and the gate metal layer are disposed on the semiconductor substrate. The transistor device is disposed in the semiconductor substrate under the source metal layer. The heavily doped region, the capacitor dielectric layer and the conductive layer constitute a capacitor structure, disposed under the gate metal layer, and the capacitor structure is electrically connected between a source and a drain of the transistor device.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: September 4, 2012
    Assignee: Sinopower Semiconductor Inc.
    Inventor: Wei-Chieh Lin
  • Patent number: 8169022
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 1, 2012
    Assignee: SS SC IP, LLC
    Inventors: Lin Cheng, Michael Mazzola
  • Patent number: 8058674
    Abstract: A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 15, 2011
    Assignee: Moxtek, Inc.
    Inventors: Derek Hullinger, Keith Decker
  • Publication number: 20110260233
    Abstract: The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.
    Type: Application
    Filed: September 20, 2010
    Publication date: October 27, 2011
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Patent number: 7944017
    Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: May 17, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuo Hatamoto, Yoshiaki Matsumiya
  • Patent number: 7928469
    Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 19, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keiko Fujihira, Naruhisa Miura, Kenichi Ohtsuka, Masayuki Imaizumi
  • Publication number: 20110068376
    Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 24, 2011
    Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
  • Patent number: 7825441
    Abstract: A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ebenezer E. Eshun, Jeffrey B. Johnson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
  • Patent number: 7741695
    Abstract: Extending from an upper surface of an n? semiconductor layer on a p? semiconductor substrate to the interface between the n? semiconductor layer and the p? semiconductor substrate, a p+ impurity region is provided. The p+ impurity region defines a high-potential island region, a low-potential island region and a slit region in the n? semiconductor layer. The n? semiconductor layer in the high-potential island region and the n? semiconductor layer in the low-potential island region are connected by the n? semiconductor layer in the slit region, and a logic circuit is formed in the n? semiconductor layer in the high-potential island region. A width in the direction of Y axis of the n? semiconductor layer in the slit region is set to be narrower than a width in the direction of the Y axis of the n? semiconductor layer in the high-potential island region.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: June 22, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuhiro Shimizu
  • Patent number: 7736961
    Abstract: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 15, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Steven L. Merchant, Philip L. Hower, Scott Paiva
  • Patent number: 7732887
    Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 8, 2010
    Assignee: Virage Logic Corporation
    Inventors: Yanjun Ma, Ronald A. Oliver, Todd E. Humes, Jaideep Mavoori
  • Patent number: 7700971
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on the same SiC semiconductor substrate, with the MOSFET structure above the SIT structure. The SIT structure includes a p+ gate region in an n-type drift layer on an n+ SiC semiconductor substrate, and an n+ first source region on the surface of the drift layer. The MOSFET structure includes a p-well region on the surface of the first source region, a second source region formed in the p-well region, and a MOS gate structure formed in a trench extending from the second source region to the first source region. The p+ gate region and a source electrode are conductively connected.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: April 20, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 7642617
    Abstract: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: January 5, 2010
    Assignee: Agere Systems Inc.
    Inventors: Alan Sangone Chen, Daniel J. Dolan, Jr., David W. Kelly, Daniel Charles Kerr, Stephen C. Kuehne
  • Patent number: 7642566
    Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 5, 2010
    Assignee: DSM Solutions, Inc.
    Inventors: Madhukar B. Vora, Ashok Kumar Kapoor
  • Patent number: 7629632
    Abstract: In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one on another on the AlGaN barrier layer 104. Since the p-type polycrystalline SiC layer 109 is relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 8, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: John Twynam
  • Patent number: 7560755
    Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: July 14, 2009
    Assignee: DSM Solutions, Inc.
    Inventor: Ashok Kumar Kapoor
  • Patent number: 7527994
    Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: May 5, 2009
    Assignee: Honeywell International Inc.
    Inventors: Kalluri R. Sarma, Charles S. Chanley
  • Patent number: 7470967
    Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 30, 2008
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Igor Sankin, Janna B. Casady, Joseph N. Merrett
  • Patent number: 7465978
    Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Su Kim, Sung-Hoan Kim
  • Publication number: 20080272408
    Abstract: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 6, 2008
    Applicant: DSM SOLUTIONS, INC.
    Inventor: Madhukar B. Vora
  • Publication number: 20080230811
    Abstract: The invention relates to a semiconductor structure, especially for use in a semiconductor detector. The semiconductor structure includes a weakly doped semiconductor substrate (HK) of a first or second doping type, a highly doped drain region (D) of a second doping type, located on a first surface of the semiconductor substrate (HK), a highly doped source region (S) of the second doping type, located on the first surface of the semiconductor substrate (HK), a duct (K) extending between the source region (S) and the drain region (D), a doped inner gate region (IG) of the first doping type, which is at least partially located below the duct (K), and a blow-out contact (CL) for removing charge carriers from the inner gate region (IG). According to the invention, the inner gate region (IG) extends in the semiconductor substrate (HK) at least partially up to the blow-out contact (CL) and the blow-out contact (CL) is located on the drain end relative to the source region (S).
    Type: Application
    Filed: January 17, 2005
    Publication date: September 25, 2008
    Applicant: MAX-PLANCK-GESELLSCHAFT ZUR FORDERUNG DER WISSENSC HAFTEN e.V.
    Inventors: Peter Lechner, Gerhard Lutz, Rainer Richter, Lothar Struder
  • Publication number: 20080217664
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Publication number: 20080210988
    Abstract: In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one on another on the AlGaN barrier layer 104. Since the p-type polycrystalline SiC layer 109 is relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.
    Type: Application
    Filed: October 31, 2007
    Publication date: September 4, 2008
    Inventor: John Twynam
  • Patent number: 7417266
    Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 26, 2008
    Assignee: QSpeed Semiconductor Inc.
    Inventors: Jian Li, Daniel Chang, Ho-Yuan Yu
  • Patent number: 7378688
    Abstract: A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventor: Dominik J. Schmidt
  • Patent number: 7335952
    Abstract: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon substrate by epitaxial growth, and then an SOI layer is deposited thereon through the intermediary of a BOX layer. A junction transistor using a part of the n-type silicon layer as a channel region and a MOS transistor using the SOI layer are produced.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: February 26, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyuki Tanaka
  • Patent number: 7335928
    Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: February 26, 2008
    Assignees: Hitachi, Ltd., Denso Corporation
    Inventors: Takasumi Ohyanagi, Atsuo Watanabe, Rajesh Kumar Malhan, Tsuyoshi Yamamoto, Toshiyuki Morishita
  • Publication number: 20080001231
    Abstract: A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Patent number: 7307329
    Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: December 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Cartens Ahrens, Ulf Bartl, Bernd Eisener, Wolfgang Hartung, Christian Herzum, Raimund Peichl, Stefan Pompl, Hubert Werthmann
  • Patent number: 7304335
    Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: December 4, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magri', Ferruccio Frisina, Giuseppe Ferla, Marco Camalleri
  • Patent number: 7268394
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Publication number: 20070187715
    Abstract: A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer.
    Type: Application
    Filed: April 9, 2007
    Publication date: August 16, 2007
    Inventor: Jian Zhao
  • Patent number: 7226818
    Abstract: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively low-temperature solution-based processing achievable with the methods of the present invention permit the use of plastics in the fabricated devices.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: June 5, 2007
    Assignee: General Electric Company
    Inventors: Patrick Roland Lucien Malenfant, Ji-Ung Lee, Yun Li, Walter Vladimir Cicha
  • Publication number: 20070102755
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 10, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Vance Adams, Paul Grudowski, Venkat Kolagunta, Brian Winstead
  • Publication number: 20060186434
    Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
    Type: Application
    Filed: April 17, 2006
    Publication date: August 24, 2006
    Applicant: STMICROELECTRONICS S.r.I.
    Inventors: Angelo MAGRI', Ferruccio FRISINA, Giuseppe FERLA, Marco CAMALLERI