With Buried Channel (epo) Patents (Class 257/E29.27)
  • Semiconductor device
    Patent number: 7271447
    Abstract: A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 18, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Teruo Takizawa, Kei Kanemoto, Juri Kato, Toshiki Hara
  • Integrated circuit devices having buried insulation layers and methods of forming the same
    Patent number: 7081391
    Abstract: An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: July 25, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeong-chan Lee, Si-young Choi, Jong-ryeol Yoo, Yong-hoon Son, In-soo Jung, Deok-hyung Lee