Abstract: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.

Abstract: A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

Abstract: A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer.

Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.

Abstract: Nano-electromechanical device having an electrically conductive nano-cantilever wherein the nano-cantilever has a free end that is movable relative to an electrically conductive substrate such as an electrode of a circuit. The circuit includes a power source connected to the electrode and to the nano-cantilever for providing a pull-in or pull-out voltage therebetween to effect bending movement of the nano-cantilever relative to the electrode. Feedback control is provided for varying the voltage between the electrode and the nano-cantilever in response to the position of the cantilever relative to the electrode. The device provides two stable positions of the nano-cantilever and a hysteresis loop in the current-voltage space between the pull-in voltage and the pull-out voltage.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

Abstract: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material, which is subsequently planarized to form a buried strap in the deep trench and a buried contact via outside the deep trench. The simultaneous formation of the buried strap and the buried contact via enables formation of a deep trench capacitor in the SOI substrate in an economic and efficient manner.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: A field effect transistor includes a silicon substrate, a source electrode and a drain electrode which are formed in upper portions of the silicon substrate, and an insulator film, a PCMO film, and a gate electrode which are formed on part of the silicon substrate sandwiched between the source electrode and the drain electrode. Data writing is performed by changing a voltage level of a write voltage applied to the PCMO film, and data reading is performed by applying a read voltage to the PCMO film and detecting a drain current.

Abstract: A semiconductor device may include a capacitor and a transistor on a silicon-on-insulator (SOI) substrate and a method for manufacturing the semiconductor device may include forming such a structure. A semiconductor device, formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, may include a capacitor including one electrode formed in a doped region of the first silicon layer and the other electrode formed in a well region of the second silicon layer.

Abstract: A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

Abstract: An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

Abstract: A high voltage capacitor and a manufacture method thereof are provided. The high voltage capacitor comprises a double diffused drain layer, an oxide layer and a poly-crystal silicon layer. The double diffused drain layer is used as a bottom electrode plate of a high voltage capacitor. The oxide layer is formed on the double diffused drain layer, and is completely overlapped on the double diffused drain layer. The poly-crystal silicon layer is formed on the oxide layer, and is used as a top electrode plate of the high voltage capacitor.

Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

Abstract: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (approximately 90% between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

Abstract: The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers being substantially orthogonal relative to first, second and third rows of contact plugs. An opening is etched which passes through each of the conductive layers within the plurality of conductive layers. The opening is disposed laterally between the first and second row of contact plugs. After etching the opening a dielectric material is deposited over the plurality of conductive layers and a second conductive material is deposited over the dielectric material. The invention includes an electronic system including a processor and a memory operably associated with the processor. The memory device has a memory array which includes double-pitched capacitors.

Abstract: In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

Abstract: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.

Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

Abstract: An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap.

Abstract: Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both.

Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

Abstract: A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.

Abstract: A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An oxide layer may be formed over the substrate, the oxide layer having an opening that exposes a portion of the high concentration diffusion junction region. A first polysilicon plate may be formed over a portion of the oxide layer and spaced from the opening, and a nitride layer may be formed over a portion of the first polysilicon plate. A sidewall may be formed over a side of the first polysilicon layer, over a side of the nitride layer, and over a portion of the oxide layer between the side of the polysilicon layer and the opening. A second polysilicon plate may be formed over the nitride layer, over the sidewall, and over the high concentration diffusion junction region.

Abstract: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described.

Abstract: A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality of electrical contacts (24) being exposed on opposing sides of the package (10). Features (30) are formed into electrically inactive portions of the integrated circuit die (12) to seal moisture paths and relieve packaging stress. The features (30) are formed by forming a trough (54) partially through the backside (56) of the wafer (40) in alignment with a saw street (48), the trough (54) having a first width; and forming a channel (62) extending from the trough (54) to the electrically active face (42) to thereby singulate the integrated circuit device member, the channel (62) having a second width that is less than the first width. (Drawing FIG.

Abstract: A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and forming a cap over the nanotubes.

Abstract: Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Abstract: A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon containing carbon or SiGe containing carbon, and silicide layers provided on the cap layers, and formed of nickel silicide or nickel-platinum alloy silicide.

Abstract: A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the first device and includes a micrometer-scale or smaller wire extending through the second device to a position in proximity to the surface of the second device. The first and second devices are displaceable between first and second positions relative to each other. The wire is not substantially electrically coupled to the doped semiconductor region in the first position and the wire is substantially electrically coupled to the doped semiconductor region in the second position. A potential applied to the wire affects the conductivity of the doped semiconductor region in the second position.

Abstract: A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo implant at an angle to form a halo profile having low dopant concentration near a gate dielectric under the gate structure. The structure includes an underlying wafer or substrate and an angled gate spacer having an upper portion and an angled lower portion. The upper portion is structured to prevent halo dopants from penetrating an inversion layer of the structure. The structure further includes a low concentration halo dopant within a channel of a gate structure.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Abstract: An improved solution for performing switching, routing, power limiting, and/or the like in a circuit, such as a radio frequency (RF) circuit, is provided. A semiconductor device that includes at least two electrodes, each of which forms a capacitor, such as a voltage-controlled variable capacitor, with a semiconductor channel of the device is used to perform the desired functionality in the RF circuit. The device includes electrodes that can provide high power RF functionality without the use of ohmic contacts or requiring annealing.

Abstract: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Abstract: A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

Abstract: Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film, and a third metal film including an electrically conductive metal coupled with the second noble metal film, wherein the first, second, and third metal films form one or more contacts having reduced specific contact resistance between the first semiconductor substrate and the one or more contacts.

Abstract: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film.

Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.

Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Abstract: A design structure of a trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The design structure resulting from the means for fabricating the trench capacitor includes the methods of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.

Abstract: A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.