In Different Semiconductor Regions (e.g., Cu 2 X/cdx Heterojunction And X Being Group Vi Element) (epo) Patents (Class 257/E31.005)
  • Patent number: 8928036
    Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 6, 2015
    Assignee: California Institute of Technology
    Inventors: David Z. Ting, Cory J. Hill, Alexander Seibel, Sumith Y. Bandara, Sarath D. Gunapala
  • Patent number: 8723019
    Abstract: A solar cell including: a silicon (Si) substrate; a buffer layer disposed on a side of the silicon substrate; a germanium (Ge) junction disposed on a side of the buffer layer opposite the silicon substrate; a first electrode electrically connected to the germanium junction; and a second electrode electrically connected to the germanium junction, wherein the buffer layer has a lattice constant that increases in a direction from the silicon substrate to the germanium junction.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ho Kim
  • Publication number: 20140053894
    Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Patent number: 8642884
    Abstract: Low-temperature sulfurization/selenization heat treatment processes for photovoltaic devices are provided. In one aspect, a method for fabricating a photovoltaic device is provided. The method includes the following steps. A substrate is provided that is either (i) formed from an electrically conductive material or (ii) coated with at least one layer of a conductive material. A chalcogenide absorber layer is formed on the substrate. A buffer layer is formed on the absorber layer. A transparent front contact is formed on the buffer layer. The device is contacted with a chalcogen-containing vapor having a sulfur and/or selenium compound under conditions sufficient to improve device performance by filling chalcogen vacancies within the absorber layer or the buffer layer or by passivating one or more of grain boundaries in the absorber layer, an interface between the absorber layer and the buffer layer and an interface between the absorber layer and the substrate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Brian Mitzi, Teodor Krassimirov Todorov
  • Patent number: 8486830
    Abstract: A via forming method that includes forming via-holes in a substrate is provided. The method includes putting the substrate, having the via-holes, in a first solution to fill the via-holes with the first solution. Metal particles are sunk into the via-holes by supplying a second solution containing the metal particles to the first solution. A first curing process of heat-treating the substrate is performed so as to form vias in the via-holes. A multi-chip package that includes the substrate having the vias is also provided.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 16, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dong Pyo Kim, Kyu Ha Baek, Kun Sik Park, Lee Mi Do
  • Publication number: 20130146133
    Abstract: A thin-film photovoltaic solar cell device is disclosed. A transparent conductive oxide (TCO) layer is disposed on a substrate as a front contact. A window layer is disposed on the TCO layer. A metal oxide layer is disposed on the window layer. An absorber layer is disposed on the metal oxide layer. A back contact layer is disposed on the absorber layer. In one embodiment, the device includes a high resistance barrier (HRT) layer interposed between the window layer and the TCO layer.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: BATTELLE MEMORIAL INSTITUTE
    Inventors: John P. Lemmon, Evgueni Polikarpov, Wendy D. Bennett
  • Publication number: 20130112275
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130082241
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart
  • Publication number: 20130062663
    Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Inventors: Ping Yuan, Xiaogang Bai, Rengarajan Sudharsanan
  • Publication number: 20130061903
    Abstract: Low-temperature sulfurization/selenization heat treatment processes for photovoltaic devices are provided. In one aspect, a method for fabricating a photovoltaic device is provided. The method includes the following steps. A substrate is provided that is either (i) formed from an electrically conductive material or (ii) coated with at least one layer of a conductive material. A chalcogenide absorber layer is formed on the substrate. A buffer layer is formed on the absorber layer. A transparent front contact is formed on the buffer layer. The device is contacted with a chalcogen-containing vapor having a sulfur and/or selenium compound under conditions sufficient to improve device performance by filling chalcogen vacancies within the absorber layer or the buffer layer or by passivating one or more of grain boundaries in the absorber layer, an interface between the absorber layer and the buffer layer and an interface between the absorber layer and the substrate.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: David Brian Mitzi, Teodor Krassimirov Todorov
  • Publication number: 20130056059
    Abstract: Described are new ohmic contact materials and diffusion barriers for Group IBIIIAVIA based solar cell structures, which eliminate two way diffusion while preserving the efficient ohmic contacts between the substrate and the absorber layers.
    Type: Application
    Filed: July 3, 2012
    Publication date: March 7, 2013
    Inventors: James Freitag, Mustafa Pinarbasi
  • Patent number: 8390025
    Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 5, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Ann Gabrys, Peter J. Hopper, William French, Kyuwoon Hwang
  • Publication number: 20130034924
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Application
    Filed: October 12, 2012
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company
  • Publication number: 20130032201
    Abstract: [Problem] In the case of further stacking a window layer or the like on a buffer layer, the buffer layer and the light absorption layer are likely to be damaged during the formation of the window layer due to inferior moisture resistance and plasma resistance, and photoelectric conversion elements sometimes fail to achieve any satisfactory conversion efficiency in terms of reliability. [Solving Means] Provided is a photoelectric conversion element including: a light absorption layer containing a I-B group element, a III-B group element, and a VI-B group element, which is provided on a lower electrode layer; a first semiconductor layer containing a III-B group element and a VI-B group element, which is provided on the light absorption layer; and a second semiconductor layer containing an oxide of a II-B group element, which is provided on the first semiconductor layer, wherein the light absorption layer comprises a doped layer region containing the II-B group element, on the first semiconductor layer side.
    Type: Application
    Filed: April 27, 2011
    Publication date: February 7, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Satoshi Oomae, Shinichi Abe, Masato Fukudome, Takeshi Ookuma, Katsuhiko Shirasawa, Takehiro Nishimura, Daisuke Toyota, Hirotaka Sano, Keita Kurosu
  • Publication number: 20130025680
    Abstract: Processes for making a process for making a photovoltaic absorber by depositing various layers of components on a substrate and converting the components into a thin film photovoltaic absorber material. Processes for depositing an ink containing compounds having the formula MB(ER)3 wherein MB is In, Ga or Al, and polymeric precursor compounds.
    Type: Application
    Filed: September 29, 2012
    Publication date: January 31, 2013
    Applicant: PRECURSOR ENERGETICS, INC.
    Inventor: Precursor Energetics, Inc.
  • Patent number: 8362460
    Abstract: A multi junction solar cell having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The solar cell includes an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by the AlAs nucleating layer. The AlAs nucleating layer provides improved morphology of the solar cell and a means to control the position of a p-n junction near the surface of the group IV substrate through diffusion of As and/or P and near the bottom of the III/V structure through minimized diffusion of the group IV element.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: January 29, 2013
    Assignee: Cyrium Technologies Incorporated
    Inventors: Norbert Puetz, Simon Fafard, Bruno J. Riel
  • Patent number: 8362494
    Abstract: An electro-optic device is disclosed. The electro-optic device includes an insulating layer, a first semiconducting region disposed above the insulating layer and being doped with doping atoms of a first conductivity type, a second semiconducting region disposed above the insulating layer and being doped with doping atoms of a second conductivity type and an electro-optic active region disposed above the insulating layer and between the first semiconducting region and the second semiconducting region. The electro-optic active region includes a first partial active region and a second partial active region and an insulating structure in between. The insulating structure extends perpendicular to the surface of the insulating layer such that there is no overlap of the first partial active region and the second partial active region in the direction perpendicular to the surface of the insulating layer. A method for manufacturing is also disclosed.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: January 29, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Guo-Qiang Patrick Lo, Kee-Soon Darryl Wang, Wei-Yip Loh, Mingbin Yu, Junfeng Song
  • Patent number: 8354693
    Abstract: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Daisuke Ueda, Toshinobu Matsuno
  • Publication number: 20120315721
    Abstract: Methods of manufacturing a solar cell module are provided. The method may include forming lower electrodes on a substrate, forming a light absorption layer on the lower electrodes and the substrate, patterning the light absorption layer to form a trench exposing the lower electrodes, and forming window electrodes using a conductive film. The conductive film extends from a top surface of the light absorption layer to a bottom of the trench along one-sidewall of the trench and is divided at another-sidewall of the trench.
    Type: Application
    Filed: May 18, 2012
    Publication date: December 13, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Rae-Man PARK
  • Publication number: 20120286328
    Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.
    Type: Application
    Filed: January 11, 2011
    Publication date: November 15, 2012
    Applicant: IRSPEC CORPORATION
    Inventors: Katsuhiko Nishida, Mutsuo Ogura
  • Patent number: 8304807
    Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: November 6, 2012
    Assignee: Intel Corporation
    Inventors: Timothy J. Maloney, Steven S. Poon
  • Publication number: 20120273839
    Abstract: A semiconductor wafer includes a base wafer, a sacrificial layer that is lattice-matched or pseudo lattice-matched to the base wafer, a first crystal layer that is formed on the sacrificial layer and made of an epitaxial crystal of SixGe1-x, (0?x<1), and a second crystal layer that is formed on the first crystal layer and made of an epitaxial crystal of a group 3-5 compound semiconductor having a larger band gap than the first crystal layer. The base wafer is, for example, made of single-crystal GaAs. The sacrificial layer is, for example, made of an epitaxial crystal of InmAlnGa1-m-nAs (0?m<1, 0<n?1, 0<n+m?1).
    Type: Application
    Filed: June 22, 2012
    Publication date: November 1, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Hisashi YAMADA, Tomoyuki TAKADA
  • Publication number: 20120255599
    Abstract: A photovoltaic structure including a nanocone-based three-dimensional interdigitated p-n junction is provided in the present invention. The three-dimensional p-n junction is at the interface between n-type oxide semiconductor nanocones and a p-type semiconductor material that functions as a matrix embedding the nanocones. The nanocone-based three-dimensional p-n junction allows efficient minority carriers being extracted from photo-absorber and crossing across the p-n junction, and generates completely-depleted regions throughout the nanocones and the matrix around the nanocones for efficient charge collection. Further, the bandgap energies of the p-doped semiconductor material can be tuned to match the solar light spectrum by mixing related elements. Further, the high temperature pulses can be used to remove defects in the junction interfaces and sintering nanoparticle matrix.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicant: UT-BATTELLE, LLC
    Inventors: Jun Xu, Sang Hyun Lee, David Barton Smith, Xiaoguang Zhang, Chad E. Duty
  • Publication number: 20120255608
    Abstract: The back-surface-field type of heterojunction solar cell according to the present invention comprises a crystalline silicon substrate of a first conductivity type, an intrinsic layer and an amorphous silicon layer of the first conductivity type which are laminated in sequence on the front surface of the substrate, an anti-reflective film laminated on the amorphous silicon of the second conductivity type, junction regions of the first conductivity type and junction regions of the second conductivity type which are formed to a predetermined depth on the inside of the substrate from the rear surface of the substrate, and first-conductivity-type electrodes and second-conductivity-type electrodes which are respectively provided on the junction regions of the first conductivity type and the junction regions of the second conductivity type; wherein the first-conductivity-type electrodes and the second-conductivity-type electrodes are disposed alternately.
    Type: Application
    Filed: December 17, 2010
    Publication date: October 11, 2012
    Applicant: HYUNDAI HEAVY INDUSTRIES CO., LTD.
    Inventors: Su Mi Yang, Sung Bong Roh, Seok Hyun Song
  • Publication number: 20120240987
    Abstract: A semiconductor device structure having increased photogenerated current density, and increased current output is disclosed. The device includes low bandgap absorber regions that increase the range of wavelengths at which photogeneration of charge carriers takes place, and for which useful current can be collected. The low bandgap absorber regions may be strain balanced by strain-compensation regions, and the low bandgap absorber regions and strain-compensation regions may be formed from the same ternary semiconductor family. The device may be a solar cell, subcell, or other optoelectronic device with a metamorphic or lattice-mismatched base layer, for which the low bandgap absorber region improves the effective bandgap combination of subcells and current balance within the multijunction cell, for higher efficiency conversion of the solar spectrum.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Applicant: THE BOEING COMPANY
    Inventors: Richard R. KING, Christopher M. FETZER, Dimitri D. KRUT, Nasser H. KARAM
  • Patent number: 8212285
    Abstract: The invention specifies a radiation detector for detecting radiation (8) according to a predefined spectral sensitivity distribution (9) that exhibits a maximum at a predefined wavelength ?0, comprising a semiconductor body (1) with an active region (5) serving to generate a detector signal and intended to receive radiation, in which according to one embodiment the active region (5) includes a plurality of functional layers (4a, 4b, 4c, 4d) that have different band gaps and/or thicknesses and are implemented such that they (4a, 4b, 4c, 4d) at least partially absorb radiation in a range of wavelengths greater than ?0. According to a further embodiment, disposed after the active region is a filter layer structure (70) comprising at least one filter layer (7, 7a, 7b, 7c), said filter layer structure determining the short-wave side (101) of the detector sensitivity (10) according to the predefined spectral sensitivity distribution (9) by absorbing wavelengths smaller than ?0.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 3, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Arndt Jaeger, Peter Stauβ, Reiner Windisch
  • Publication number: 20120111395
    Abstract: A solar cell including: a silicon (Si) substrate; a buffer layer disposed on a side of the silicon substrate; a germanium (Ge) junction disposed on a side of the buffer layer opposite the silicon substrate; a first electrode electrically connected to the germanium junction; and a second electrode electrically connected to the germanium junction, wherein the buffer layer has a lattice constant that increases in a direction from the silicon substrate to the germanium junction.
    Type: Application
    Filed: March 29, 2011
    Publication date: May 10, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong-Ho KIM
  • Publication number: 20120073658
    Abstract: In a heterojunction solar cell, a semiconductor A is bonded to a different conductivity type semiconductor B having an electron affinity a2 which is larger than an electron affinity a1 of the semiconductor A. The semiconductor A and the semiconductor B are lattice-matched to each other with a mismatch ratio of less than 1%, respectively. In a method for fabricating the heterojunction solar cell, the semiconductor A and the semiconductor B are lattice-matched to each other with a mismatch ratio of less than 1% respectively, and the semiconductor A is made of p-type silicon with a p-type germanium layer formed on the surface thereof, and n-type GaP is formed after removing an oxide film by removing the germanium layer.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 29, 2012
    Applicant: Takashi Tomita
    Inventor: Takashi TOMITA
  • Publication number: 20120060922
    Abstract: A non-sintered structure. The non-sintered structure includes a first non-sintered nanocrystal layer, and a second non-sintered nanocrystal layer wherein the first layer and the second layer are configured to interact electronically.
    Type: Application
    Filed: March 2, 2009
    Publication date: March 15, 2012
    Applicant: The Regents of the University of California
    Inventors: Cyrus Wadia, Yue Wu, Paul A. Alivisatos
  • Publication number: 20120040486
    Abstract: A method for manufacturing TF-PV material by providing a TF-PV material layer having a degree of crystallinity, and irradiating a surface region of the TF-PV material layer using a laser source having irradiation parameter selected such that the degree of crystallinity is increased at least at a top layer of the surface region.
    Type: Application
    Filed: December 21, 2009
    Publication date: February 16, 2012
    Applicant: EXCICO GROUP - RCH (RESEARCH CAMPUS HASSELT)
    Inventor: Simon Rack
  • Publication number: 20120031491
    Abstract: A single P-N junction solar cell is provided having two depletion regions for charge separation while allowing the electrons and holes to recombine such that the voltages associated with both depletion regions of the solar cell will add together. The single p-n junction solar cell includes an alloy of either InGaN or InAlN formed on one side of the P-N junction with Si formed on the other side in order to produce characteristics of a two junction (2J) tandem solar cell through only a single P-N junction. A single P-N junction solar cell having tandem solar cell characteristics will achieve power conversion efficiencies exceeding 30%.
    Type: Application
    Filed: October 17, 2011
    Publication date: February 9, 2012
    Applicant: RoseStreet Labs Energy, LLC
    Inventors: Wladyslaw Walukiewicz, Joel W. Ager, III, Kin Man Yu
  • Publication number: 20120012811
    Abstract: Techniques are disclosed for improving the quantum efficiency of photocathode devices. The techniques allow for an increase in the optical thickness of the photocathode device, while simultaneously allowing for an increase in the probability of electron escape into the vacuum of the device. The techniques are particularly useful in detector and imaging. In one embodiment, a photocathode device is provided that has an array of corner cubes fabricated in a surface of the photocathode. The corner cube array is made of the same material as the photocathode layer. The device may be, for example, a detector or image intensifier that operates in the UV, visible, and IR light spectrums, and may further include a gain medium, anode, and readout device. Techniques for forming the device are also provided.
    Type: Application
    Filed: January 20, 2010
    Publication date: January 19, 2012
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventors: Michael E. DeFlumere, Paul W. Schoeck
  • Publication number: 20110297968
    Abstract: A rod-shaped semiconductor device having a light-receiving or light-emitting function is equipped with a rod-shaped substrate made of p-type or n-type semiconductor crystal, a separate conductive layer which is formed on a part of the surface of the substrate excluding a band-shaped part parallel to the axis of the substrate and has a different conduction type from the conduction type of the substrate, a pn-junction formed with the substrate and separate conductive layer, a band-shaped first electrode which is formed on the surface of the band-shaped part on the substrate and ohmic-connected to the substrate, and a band-shaped second electrode which is formed on the opposite side of the first electrode across the shaft of said substrate and ohmic-connected to the separate conductive layer.
    Type: Application
    Filed: August 2, 2011
    Publication date: December 8, 2011
    Applicant: KYOSEMI CORPORATION
    Inventor: Josuke Nakata
  • Patent number: 8044476
    Abstract: A radiation detector comprising a II-VI compound semiconductor substrate that absorbs radiation having a first energy, a II-VI compound semiconductor layer of a first conductivity type provided on a main surface of the II-VI compound semiconductor substrate, a metal layer containing at least one of a group III element and a group V element provided on the II-VI compound semiconductor layer, a IV semiconductor layer having a second conductivity type opposite to the first conductivity type provided on the metal layer, and a IV semiconductor substrate that absorbs radiation having a second energy different from the first energy provided on the IV semiconductor layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: October 25, 2011
    Assignee: National University Corporation Shizuoka University
    Inventors: Yoshinori Hatanaka, Toru Aoki
  • Patent number: 8039290
    Abstract: Methods of making a photovoltaic (PV) cell are disclosed. The methods comprise at least the steps of, providing a first component comprising a cadmium telluride (CdTe) layer comprising an interfacial region, and subjecting the first component to a functionalizing treatment in the presence of a material comprising copper.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 18, 2011
    Assignee: General Electric Company
    Inventors: Scott Feldman-Peabody, Bogdan Lita, Michael Burnash Cozens, Mehran Sadeghi, Yu Zhao, Renee Mary Whitney
  • Publication number: 20110248315
    Abstract: An electrode comprising a plurality of structured pillars dispersed across a base contact and its method of manufacture are described. In one embodiment the structured pillars are columnar structures having a circular cross-section and are dispersed across the base surface as a uniformly spaced two-dimensional array. The height, diameter, and separation of the structured pillars are preferably on the nanometer scale and, hence, electrodes comprising the pillars are identified as nanostructured pillar electrodes. The nanostructured pillars may be formed, for example, by deposition into or etching through a surface template using standard lithography processes. Structured pillar electrodes offer a number of advantages when incorporated into optoelectronic devices such as photovoltaic cells. These include improved charge collection efficiency via a reduction in the carrier transport distance and an increase in electrode-photoactive layer interface surface area.
    Type: Application
    Filed: August 14, 2009
    Publication date: October 13, 2011
    Applicant: BROOKHAVEN SCIENCE ASSOCIATES
    Inventors: Chang-Yong Nam, Charles T. Black, Ioana R. Gearba, Jonathan Edward Allen
  • Patent number: 8030684
    Abstract: The present invention relates to a stable mesa-type photodetector with lateral diffusion junctions. The invention has found that without resorting to the complicated regrowth approach, a simple Zn diffusion process can be used to create high-quality semiconductor junction interfaces at the exposed critical surface or to terminate the narrow-bandgap photon absorption layers. The invention converts the epi material layers near or at the vicinity of the etched mesa trench or etched mesa steps into a different dopant type through impurity diffusion process. Preferably the diffused surfaces are treated with a subsequent surface passivation. This invention can be applied to both top-illuminating and bottom-illuminating configurations.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: October 4, 2011
    Assignee: JDS Uniphase Corporation
    Inventors: Syn-Yem Hu, Zhong Pan
  • Publication number: 20110214725
    Abstract: A photovoltaic device can include a graded bandgap buffer layer.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 8, 2011
    Applicant: First Solar, Inc.
    Inventor: Markus E. Beck
  • Publication number: 20110139227
    Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel heterojunction interposed between the first and second subcells. A first side of the tunnel heterojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type, is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel heterojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type, and is comprised of a highly doped Group II-VI semiconductor material. The tunnel heterojunction permits photoelectric series current to flow through the subcells.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: EPIR TECHNOLOGIES, INC.
    Inventors: Sivalingam SIVANANTHAN, Michael CARMODY, Robert W. BOWER, Shubhrangshu MALLICK, James GARLAND
  • Publication number: 20110121319
    Abstract: Light emitting devices and methods of fabricating the same are disclosed. The light emitting device includes a light emitting diode (LED) that emits blue or UV light and is attached to a semiconductor construction. The semiconductor construction includes a re-emitting semiconductor construction that includes at least one layer of a II-VI compound and converts at least a portion of the emitted blue or UV light to longer wavelength light. The semiconductor construction further includes an etch-stop construction that includes an AlInAs or a GaInAs compound. The etch-stop is capable of withstanding an etchant that is capable of etching InP.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 26, 2011
    Inventors: Michael A. Haase, Thomas J. Miller, Xiaoguang Sun
  • Publication number: 20110056544
    Abstract: A solar cell is disclosed. The solar cell includes a substrate containing first impurities of a first conductive type, an emitter layer containing second impurities of a second conductive type opposite the first conductive type, a first electrode electrically connected to the emitter layer, and a second electrode electrically connected to the substrate. The emitter layer and the substrate form a p-n junction. A doping concentration of the second impurities of the emitter layer linearly or nonlinearly changes depending on a depth of a position within the emitter layer.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 10, 2011
    Applicant: LG ELECTRONICS INC.
    Inventors: Kwangsun JI, Heonmin LEE, Wonseok CHOI, Junghoon CHOI, Hyunjin YANG
  • Patent number: 7892879
    Abstract: This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: February 22, 2011
    Assignee: Qinetiq Limited
    Inventors: Louise Buckle, John W Cairns, Jean Giess, Neil T Gordon, Andrew Graham, Janet E Hails, David J Hall, Colin J Hollier, Graham J Pryce, Andrew J Wright
  • Patent number: 7847317
    Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: December 7, 2010
    Assignee: Intel Corporation
    Inventors: Timothy J. Maloney, Steven S. Poon
  • Publication number: 20100295095
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Inventor: Philip KLIPSTEIN
  • Publication number: 20100282306
    Abstract: A method of manufacturing a solar cell by providing a germanium semiconductor growth substrate; and depositing on the semiconductor growth substrate a sequence of layers of semiconductor material forming a solar cell, including a subcell composed of a group IV/III-V hybrid alloy.
    Type: Application
    Filed: May 8, 2009
    Publication date: November 11, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Paul Sharps, Fred Newman
  • Patent number: 7808065
    Abstract: A semiconductor photosensitive element comprises: a semiconductor substrate of a first conductivity type; a first light absorption layer, a first semiconductor layer of a second conductivity type, a first semiconductor layer of the first conductivity type, a second light absorption layer, and a second semiconductor layer of a second conductivity type, arranged in this order on the semiconductor substrate; a first electrode connected the second semiconductor layer of the second conductivity type; a second electrode connected to the semiconductor substrate; and a third electrode electrically connecting the first semiconductor layer of the first conductivity type to the first semiconductor layer of the second conductivity type. The third electrode is located outside a light detection region for detecting optical signals.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eitaro Ishimura, Masaharu Nakaji
  • Publication number: 20100240171
    Abstract: A multijunction solar cell is fabricated according to an embodiment by providing a substrate, depositing a nucleation first layer over and directly in contact with the substrate, depositing a second layer containing an arsenic dopant over the nucleation layer and depositing a sequence of layers over the second layer forming at least one solar subcell. The nucleation layer serves as a diffusion barrier to the arsenic dopant such that diffusion of the arsenic dopant into the substrate is limited in depth by the nucleation layer.
    Type: Application
    Filed: April 8, 2010
    Publication date: September 23, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
  • Patent number: 7750366
    Abstract: A solid-state imaging element includes a layered substrate made of silicon and composed of, for example, an N-type substrate, a P-type layer, and an N-type layer. In the layered substrate, an imaging region in which a plurality of pixels are arranged and a peripheral circuit region are formed. A recess reaching the reverse face of the P-type layer is formed in a reverse face portion of the layered substrate in the imaging region, and a reflective film is formed on at least the inner face of the recess. Light is reflected on the reverse face and the obverse face of the layered substrate.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: July 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Toru Okino, Mitsuyoshi Mori
  • Publication number: 20100072514
    Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 25, 2010
    Applicant: California Institute of Technology
    Inventors: David Z. Ting, Cory J. Hill, Alexander Soibel, Sumith V. Bandara, Sarath D. Gunapala
  • Patent number: 7683397
    Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a mesa structure defined in a first type of semiconductor. The first type of semiconductor material includes an absorption region optically coupled to receive and absorb an optical beam. The apparatus also includes a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material. The planar region includes a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region. The high electric field is to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Gadi Sarid, Yimin Kang, Alexandre Pauchard