Comprising Only Group Iv-vi Or Ii-iv-vi Chalcogenide Compound (e.g., Pbsnte) (epo) Patents (Class 257/E31.029)
  • Patent number: 9992430
    Abstract: A per-pixel performance improvement is described for combined image sensor arrays that measure infrared and visible light. One embodiment is a method that includes forming an array of photodetectors on a silicon substrate, treating a subset of the photodetectors to improve sensitivity to infrared light, and finishing the photodetector array to form an image sensor.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 5, 2018
    Assignee: INTEL CORPORATION
    Inventors: Richmond Hicks, Khaled Ahmed
  • Patent number: 9472271
    Abstract: A method for pre-programming a matrix of phase-change memory cells, including a phase-change material positioned between two conducting electrodes and able to be reversely electrically modified so as to vary the resistivity of the memory cell. A dielectric layer is provided with the memory cell having an original resistive state at the end of the memory cell production process. A pre-programming of the matrix is executed prior to mounting a component containing the matrix on a support. A breakdown voltage is applied to a selection of memory cells so that, for each one of the selected cells, the layer of the dielectric material breaks down to bring the cell from the original resistive state to a second resistive state.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 18, 2016
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Institut Polytechnique de Grenoble
    Inventors: Quentin Hubert, Carine Jahan
  • Patent number: 8999745
    Abstract: A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. The diode line and the projection are formed of a single layer to be in continuity with each other.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Il Yong Lee
  • Patent number: 8962378
    Abstract: A method for manufacturing a photodiode including the steps of providing a substrate, solution depositing a quantum nanomaterial layer onto the substrate, the quantum nanomaterial layer including a number of quantum nanomaterials having a ligand coating, and applying a thin-film oxide layer over the quantum nanomaterial layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: February 24, 2015
    Assignee: The Boeing Company
    Inventors: Larken E. Euliss, G. Michael Granger, Keith J. Davis, Nicole L. Abueg, Peter D. Brewer, Brett Nosho
  • Patent number: 8890107
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8865514
    Abstract: The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. Upon the application of heat, the titanium may react with the tellurium to a controlled extent to reduce the concentration of tellurium in the chalcogenide film.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Camillo Bresolin, Silvia Rossini
  • Patent number: 8866120
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8859323
    Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 300 C and about 400 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. A partial selenization is performed at a temperature between about 300 C and about 400 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 400 C and about 550 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8860111
    Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: October 14, 2014
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam, Matthew J. Breitwisch
  • Patent number: 8859344
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8828785
    Abstract: Techniques for producing a single-crystal phase change material and the incorporation of those techniques in an electronic device fabrication process flow are provided. In one aspect, a method of fabricating an electronic device is provided which includes the following steps. A single-crystal phase change material is formed on a first substrate. At least one first electrode in contact with a first side of the single-crystal phase change material is formed. The single-crystal phase change material and the at least one first electrode in contact with the first side of the single-crystal phase change material form a transfer structure on the first substrate. The transfer structure is transferred to a second substrate. At least one second electrode in contact with a second side of the single-crystal phase change material is formed. A single-crystal phase change material-containing structure and electronic device are also provided.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Simone Raoux
  • Patent number: 8796661
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej Sandhu
  • Patent number: 8772077
    Abstract: The present invention concerns a method of forming a chalcogenide thin film for a phase-change memory. In the method of forming a chalcogenide thin film according to the present invention, a substrate with a pattern formed is loaded into a reactor, and a source gas is supplied onto the substrate. Here, the source gas includes at least one source gas selected from germanium (Ge) source gas, gallium (Ga) source gas, indium (In) source gas, selenium (Se) source gas, antimony (Sb) source gas, tellurium (Te) source gas, tin (Sn) source gas, silver (Ag) source gas, and sulfur (S) source gas. A first purge gas is supplied onto the substrate in order to purge the source gas supplied onto the substrate, a reaction gas for reducing the source gas is then supplied onto the substrate, and a second purge gas is supplied onto the substrate in order to purge the reaction gas supplied onto the substrate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: July 8, 2014
    Assignee: IPS Ltd.
    Inventors: Ki-Hoon Lee, Jung-Wook Lee, Dong-Ho You
  • Patent number: 8759809
    Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, John K. Zahurak
  • Patent number: 8753949
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8716056
    Abstract: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: May 6, 2014
    Assignee: Ovonyx, Inc.
    Inventor: Ward Parkinson
  • Patent number: 8679914
    Abstract: A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method of forming a resistive random access memory device is also disclosed. The method comprises forming a plurality of memory cells wherein each cell of the plurality of memory cells is formed by forming a metal on a first electrode, forming a chalcogenide material on the metal by a gas cluster ion beam process, and forming a second electrode on the chalcogenide material. A method of forming another resistive random access memory device and a random access memory device including the chalcogenide material are also disclosed.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Timothy A. Quick
  • Patent number: 8637847
    Abstract: Resistive memory cells having a plurality of heaters and methods of operating and forming the same are described herein. As an example, a resistive memory cell may include a resistance variable material located between a first electrode and a second electrode, a first heater coupled to a first portion of the resistance variable material, a second heater coupled to a second portion of the resistance variable material, a third heater coupled to a third portion of resistance variable material, and a conductive material coupled to the first, second, and third heaters.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli
  • Patent number: 8633463
    Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jong-Won Lee, Kuo-Wei Chang, Michael L. McSwiney
  • Patent number: 8623694
    Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material, resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Rita J. Klein
  • Patent number: 8617916
    Abstract: A chemical bath deposition method is presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition apparatus deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited by continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The method is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: December 31, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8614114
    Abstract: A treatment object containing any one of Cu/Ga, Cu/In and Cu—Ga/In is held in a heated state at a temperature T1 for a time ?t1 in such a state that a selenium source is introduced, thereby forming a selenide. Thereafter, a sulfur source is introduced to replace the atmosphere in the system with a sulfur atmosphere. In this state, the treatment object is held in a heated state at a temperature T2 for a time ?t2. The temperature of the treatment object is then decreased to T3, and, at that temperature, the treatment object is held in a heated state for a time ?t3.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: December 24, 2013
    Assignee: Showa Shell Sekiyu K.K.
    Inventors: Hideki Hakuma, Yuri Yamaguchi, Katsuya Tabuchi, Katsumi Kushiya
  • Patent number: 8597974
    Abstract: Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Zailong Bian
  • Patent number: 8586957
    Abstract: A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Lia Krusin-Elbaum, Dennis M. Newns, Matthew R. Wordeman
  • Patent number: 8546784
    Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Kristy A. Campbell
  • Patent number: 8546783
    Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
  • Patent number: 8530878
    Abstract: Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8525244
    Abstract: A germanium (Ge) compound is provided. The Ge compound has a chemical formula GeR1xR2y. “R1” is an alkyl group, and “R2” is one of hydrogen, amino group, allyl group and vinyl group. “x” is greater than zero and less than 4, and the sum of “x” and “y” is equal to 4. Methods of forming the Ge compound, methods of fabricating a phase change memory device using the Ge compound, and phase change memory devices fabricated using the Ge compound are also provided.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Young Park, Myong-Woon Kim, Jin-Dong Kim, Choong-Man Lee, Jin-Il Lee
  • Patent number: 8525144
    Abstract: A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, Sampath Purushothaman
  • Publication number: 20130217176
    Abstract: In one embodiment, a method includes depositing a chalcogenide precursor layer onto a substrate, introducing a cover into proximity with the precursor layer, and annealing the precursor layer in proximity with of the cover, where the annealing is performed in a constrained volume, and where the presence of the cover reduces decomposition of volatile species from the precursor layer during annealing.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 22, 2013
    Applicant: AQT SOLAR, INC.
    Inventors: Mariana Rodica Munteanu, Amith Kumar Murali, Brian Josef Bartholomeusz, Vardaan Chawla
  • Publication number: 20130217177
    Abstract: In one embodiment, a method includes depositing a chalcogenide precursor layer onto a substrate, and annealing the precursor layer in the presence of a gaseous phase comprising volatile species, the partial pressure of each volatile species being approximately constant over substantially all of the surface of the precursor layer, the partial pressure of each species being between approximately 0.1 mTorr and 760 Torr, where the presence of the gaseous phase reduces decomposition of volatile species from the precursor layer during annealing.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 22, 2013
    Applicant: AQT SOLAR, INC.
    Inventors: Kaichiu Wong, Erik Sean Smith, Christ Willie Ford
  • Patent number: 8513637
    Abstract: Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include memory elements comprising programmable resistive material and self-aligned bottom electrodes. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: August 20, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8501526
    Abstract: A method for synthesizing a thin film of copper, zinc, tin, and a chalcogen species (“CZTCh” or “CZTSS”) with well-controlled properties. The method includes depositing a thin film of precursor materials, e.g., approximately stoichiometric amounts of copper (Cu), zinc (Zn), tin (Sn), and a chalcogen species (Ch). The method then involves re-crystallizing and grain growth at higher temperatures, e.g., between about 725 and 925 degrees K, and annealing the precursor film at relatively lower temperatures, e.g., between 600 and 650 degrees K. The processing of the precursor film takes place in the presence of a quasi-equilibrium vapor, e.g., Sn and chalcogen species. The quasi-equilibrium vapor is used to maintain the precursor film in a quasi-equilibrium condition to reduce and even prevent decomposition of the CZTCh and is provided at a rate to balance desorption fluxes of Sn and chalcogens.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Glenn Teeter, Hui Du, Matthew Young
  • Patent number: 8481359
    Abstract: Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Keith R. Hampton
  • Patent number: 8445887
    Abstract: A nonvolatile programmable switch device using a phase-change memory device and a method of manufacturing the same are provided. The switch device includes a substrate, a first metal electrode layer disposed on the substrate and including a plurality of terminals, a phase-change material layer disposed on the substrate and having a self-heating channel structure, the phase-change material layer having a plurality of introduction regions electrically contacting the terminals of the first metal electrode layer and a channel region interposed between the introduction regions, an insulating layer disposed on the first metal electrode layer and the phase-change material layer, a via hole disposed on the first metal electrode layer, and a second metal electrode layer disposed to fill the via hole.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: May 21, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Byoung Gon Yu, Soon Won Jung, Seung Yun Lee, Young Sam Park, Joon Suk Lee
  • Patent number: 8440498
    Abstract: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: May 14, 2013
    Assignee: Nanosolar, Inc.
    Inventors: Matthew R. Robinson, Chris Eberspacher, Jeroen K. J. Van Duren
  • Patent number: 8440535
    Abstract: A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 14, 2013
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 8415651
    Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a memory element and a first electrode having an inner surface surrounding the memory element to contact the memory element at a first contact surface. The device includes a second electrode spaced away from the first electrode, the second electrode having an inner surface surrounding the memory element to contact the memory element at a second contact surface.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: April 9, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8395192
    Abstract: A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Chung Hon Lam
  • Patent number: 8389967
    Abstract: A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, Sampath Purushothaman
  • Publication number: 20130023986
    Abstract: An artificial retina that includes: (i) a substrate; (ii) a first layer, placed onto said substrate and including photovoltaic material portions separated by at least one insulating material portion; and (iii) a second layer, placed onto said first layer and including conductive material portions separated by at least one insulating material portion. In said artificial retina, the photovoltaic material includes a titanium dioxide semiconductor.
    Type: Application
    Filed: December 7, 2010
    Publication date: January 24, 2013
    Applicants: UNIVERSITE DE STRASBOURG, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.R.S)
    Inventors: Nicolas Keller, Pierre Bernhardt, Michel Roux, Anne Kobe, Shankar Muthukonda Venkatakrishnan, Serge Picaud, Marc J. Ledoux, Valerie Keller-Spitzer, Thomas Cottineau
  • Publication number: 20130005073
    Abstract: A chemical bath deposition method and a system are presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition system deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8344350
    Abstract: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Ovonyx, Inc.
    Inventors: Wolodymyr Czubatyj, Tyler Lowrey
  • Publication number: 20120322196
    Abstract: A method of manufacturing a solid-state image sensor, comprising preparing a semiconductor substrate including a photoelectric converter and an insulating film which includes an opening and is formed in a region above the photoelectric converter, depositing a material having a refractive index higher than the insulating film in the opening, and annealing the material deposited in the opening by irradiating the material with one of light and radiation, wherein a light waveguide which is configured to guide an incident light to the photoelectric converter is formed through the depositing and the annealing.
    Type: Application
    Filed: May 22, 2012
    Publication date: December 20, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Patent number: 8330136
    Abstract: A PCM device has the composition GexTeyNzAm deposited onto a substrate, where x is about 40% to about 60%, y is about 30% to about 49%, and z is about 5% to about 20% and more preferably about 5% to about 40%. The component represented as A is optional and representative of an element of Sb, Sn, In, Ga, or Zn, and m is up to about 15%. The composition is in the form of a film, and the nitrogen allows for the substantially conformal deposition of the film onto the substrate. A CVD process for depositing the PCM comprises delivering a Ge-based precursor and a Te-based precursor in vapor form to a CVD chamber, heating and pressurizing the chamber, and depositing the film onto a substrate. In making a phase change device using this process, the film is annealed and polished.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jun-Fei Zheng, Jeffrey F. Roeder, Weimin Li, Philip S. H. Chen
  • Patent number: 8330138
    Abstract: An electronic device (100), the electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101).
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: December 11, 2012
    Assignee: NXP B.V.
    Inventors: Romain Delhougne, Michael Zandt
  • Publication number: 20120295396
    Abstract: A method for synthesizing a thin film of copper, zinc, tin, and a chalcogen species (“CZTCh” or “CZTSS”) with well-controlled properties. The method includes depositing a thin film of precursor materials, e.g., approximately stoichiometric amounts of copper (Cu), zinc (Zn), tin (Sn), and a chalcogen species (Ch). The method then involves re-crystallizing and grain growth at higher temperatures, e.g., between about 725 and 925 degrees K, and annealing the precursor film at relatively lower temperatures, e.g., between 600 and 650 degrees K. The processing of the precursor film takes place in the presence of a quasi-equilibrium vapor, e.g., Sn and chalcogen species. The quasi-equilibrium vapor is used to maintain the precursor film in a quasi-equilibrium condition to reduce and even prevent decomposition of the CZTCh and is provided at a rate to balance desorption fluxes of Sn and chalcogens.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 22, 2012
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: Glenn Teeter, Hui Du, Matthew Young
  • Publication number: 20120276683
    Abstract: A new, more economical method for preparing titania pastes for use in more efficient dye-sensitized solar cells is disclosed. The titania pastes are prepared by mixing titania nanoparticles with a titania sol including a titanium precursor. The disclosed method enables the control of titania nanoparticle concentration and morphology in the titania paste and is economical due to the relatively low reaction temperatures. The performances of dye-sensitized solar cells prepared using the disclosed titania pastes are also disclosed.
    Type: Application
    Filed: July 1, 2012
    Publication date: November 1, 2012
    Inventor: MOHAMMAD-REZA MOHAMMADI
  • Patent number: 8278639
    Abstract: A high integration phase change memory device includes a semiconductor substrate including an access device, a heating electrode formed on the access device, a phase change nano band formed on the heating electrode, and an interlayer insulating layer for supporting the phase change nano band formed in both sides of the phase change nano band.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: October 2, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Se Ho Lee
  • Patent number: 8269205
    Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance. The recording layer includes a first compound layer and a second compound layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The second compound layer contains a second compound. The second compound includes a transition element having a d-orbital partially filled with electron, and the second compound includes a void site capable of storing at least one of the first cation element and the second cation element.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kohichi Kubo, Chikayoshi Kamata, Takayuki Tsukamoto, Shinya Aoki, Takahiro Hirai, Tsukasa Nakai, Toshiro Hiraoka