Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.

Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).

Abstract: Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.

Abstract: A copper-diffusion plug 21 is provided within a pore in dielectric layer over a copper signal line. By positioning the plug below a chalcogenide region, the plug is effective to block copper diffusion upwardly into the pore and into the chalcogenide region and thus to avoid adversely affecting the electrical characteristics of the chalcogenide region.

Abstract: Methods and systems for electrochemically depositing doped metal oxide and metal chalcogenide films are disclosed. An example method includes dissolving a metal precursor into a solution, adding a halogen precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit halogen doped metal oxide or metal chalcogenide onto a substrate. Another example method includes dissolving a zinc precursor into a solution, adding an yttrium precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit yttrium doped zinc oxide onto a substrate. Other embodiments are described and claimed.

Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance by a current supplied via the first layer and the second layer. The recording layer includes a first compound layer and an insulating layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The insulating layer contains a third compound, and the third compound includes an element selected from group 1 to 4 elements and group 12 to 17 elements in the periodic table.

Abstract: Methods for laser scribing a film stack including a plurality of thin film layers on a substrate are provided. A pulse of a laser beam is applied to the film stack, where the laser beam has a power that varies as a function of time during the pulse according to a predetermined power cycle. For example, the pulse can have a pulse lasting about 0.1 nanoseconds to about 500 nanoseconds. This pulse of the laser beam can be repeated across the film stack to form a scribe line through at least one of the thin film layers on the substrate. Such methods are particularly useful in laser scribing a cadmium telluride thin-film based photovoltaic device.

Abstract: Thin film photovoltaic devices are provided that generally include a transparent conductive oxide layer on the glass, a multi-layer n-type stack on the transparent conductive oxide layer, and a cadmium telluride layer on the multi-layer n-type stack. The multi-layer n-type stack generally includes a first layer and a second layer, where the first layer comprises cadmium and sulfur and the second layer comprises cadmium and oxygen. The multi-layer n-type stack can, in certain embodiments, include additional layers (e.g., a third layer, a fourth layer, etc.). Methods are also generally provided for manufacturing such thin film photovoltaic devices.

Abstract: A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the cylindrical solid phase portion results in a more gradual transition of resistance versus programming current, enabling multilevel memories to be formed.

Abstract: To provide a transparent conductive substrate for a solar cell, which has a haze factor at the same level of conventional transparent conductive substrates for a solar cell, and a small amount of absorbed light at a wavelength region of about 400 nm by a tin oxide layer. A transparent conductive substrate for a solar cell, comprising a substrate and at least a silicon oxide layer and a tin oxide layer formed thereon in this order, wherein on the silicon oxide layer between the silicon oxide layer and the tin oxide layer, discontinuous ridge parts consisting of tin oxide and a crystalline thin layer consisting of an oxide containing substantially no tin oxide are formed.

Abstract: A method for making a semiconductor device (10) includes providing an interconnect layer (14) over an underlying layer (12), forming a first insulating layer (16) over the interconnect layer, and forming an opening (18) through the insulating layer to the interconnect layer. A first conductive layer (24) is formed over the interconnect layer and in the opening. This is performed by plating so it is selective. A second conductive layer (28) in the opening is formed by displacement by immersion. This is performed after the first conductive layer has been formed. The result is the second conductive layer is formed by a selective deposition and is effective for providing it with bridging material. A layer of bridgeable material (34) is formed over the second conductive layer and in the opening. A third conductive layer (42) is formed over the bridgeable material. The semiconductor device may be useable as a conductive bridge memory device.

Abstract: Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.

Abstract: A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

Abstract: A photovoltaic device with a low-resistance stable electrical back contact is disclosed. The photovoltaic device can have a CuTex or CuTexNy layer.

Abstract: An apparatus and method for storing information are provided, including using an integrated circuit including a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. To store information, the on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer.

Abstract: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C.

Abstract: An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed on a collector. The phase-change memory device has a phase-change material layer which is changed from an amorphous state to a crystalline state by a current, and a heating layer composed of SiGe that contacts the lower surface of the phase-change material layer.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: Sulfur-containing chalcogenide absorbers in thin film solar cell are manufactured by sequential sputtering or co-sputtering targets, one of which contains a sulfur compound, onto a substrate and then annealing the substrate. The anneal is performed in a non-sulfur containing environment and avoids the use of hazardous hydrogen sulfide gas. A sulfurized chalcogenide is formed having a sulfur concentration gradient.

Abstract: The present invention provides improved chalcogen-containing, photovoltaic structures as well as related compositions, photovoltaic devices incorporating these structures, methods of making these structures and devices, and methods of using these structures and devices. According to principles of the present invention, the adhesion of PACB compositions is improved through the use of chalcogen-containing tie layers.

Abstract: A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer.

Abstract: A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.

Abstract: Disclosed are a phase change RAM device and a method for fabricating a phase change RAM device, which can efficiently lower intensity of current required for changing a phase of a phase change layer. The method includes the steps of providing a semiconductor substrate formed with an insulating interlayer including a tungsten plug, forming a first oxide layer on the semiconductor substrate, forming a pad-type bottom electrode, which makes contact with the tungsten plug, in the first oxide layer, forming a second oxide layer on the first oxide layer including the bottom electrode, and forming a porous polystyrene pattern on the second oxide layer such that a predetermined portion of the second oxide layer corresponding to a center portion of the bottom electrode is covered with the porous polystyrene pattern.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.

Abstract: Example embodiments may provide resistive random access memory devices and/or methods of manufacturing resistive random access memory devices. Example embodiment resistive random access memory devices may include a switching device and/or a storage node connected to the switching device. The storage node may include a stack structure including a plurality of resistance change layers separated from one another and first and second electrodes each on a side wall of the stack structure. The resistance change layers may be connected to the first and the second electrodes in parallel and/or may have different switching voltages from each other.

Abstract: A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.

Abstract: A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge2Sb2+xTe5 (0.12?x?0.32), so that the crystalline state is determined as a stable single phase, not a mixed phase of a metastable phase and a stable phase, in phase transition between crystalline and amorphous states of a phase change material, and the phase transition according to increasing temperature directly transitions to the single stable phase from the amorphous state. As a result, set operation stability and distribution characteristics of set state resistances of the phase change memory device can be significantly enhanced, and an amorphous resistance can be maintained for a long time at a high temperature, i.e., around crystallization temperature, and thus reset operation stability and rewrite operation stability of the phase change memory device can be significantly enhanced.

Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract: Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.

Abstract: A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.

Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

Abstract: A method and apparatus for improving efficiency of photovoltaic cells by improving light capture between the photoelectric unit and back reflector is provided. A transition layer is formed at the interface between the photoelectric unit and transmitting conducting layer of the back reflector by adding oxygen, nitrogen, or both to the surface of the photoelectric unit or the interface between the photoelectric unit and the transmitting conducting layer. The transition layer may comprise silicon, oxygen, or nitrogen, and may be silicon oxide, silicon nitride, metal oxide with excess oxygen, metal oxide with nitrogen, or any combination thereof, including bilayers and multi-layers. The sputtering process for forming the transmitting conducting layer may feature at least one of nitrogen and excess oxygen, and may be performed by sputtering at low power, followed by an operation to form the rest of the transmitting conductive layer.

Abstract: A solar cell including a substrate, a first conductive layer, a photovoltaic layer, a second conductive layer and at least one passivation layer is provided. The first conductive layer is disposed on the substrate. The photovoltaic layer generates electron-hole pairs after receiving light, wherein the photovoltaic layer is disposed on the first conductive layer and has a plurality of doped films. The second conductive layer is disposed on the photovoltaic layer. The passivation layer is disposed onto at least one of the positions between the first conductive layer and the photovoltaic layer, between the doped films within the photovoltaic layer, and between the photovoltaic layer and the second conductive layer, so as to reduce the chance for the electron-hole pairs resulting in recombination on at least one of the surfaces of the photovoltaic layer. A manufacturing method of the solar cell is also provided.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Abstract: A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a second end of the first electrode. A resistance variable material layer is located between the first and second electrodes, and the second end of the first electrode is in contact with the resistance variable material. Methods for forming the memory element are also provided.

Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

Abstract: A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.

Abstract: Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.

Abstract: A phase-change material and a memory unit using the phase-change material are provided. The phase-change material is in a single crystalline state and includes a compound of a metal oxide or nitroxide, wherein the metal is at least one selected from a group consisting of indium, gallium and germanium. The memory unit includes a substrate; at least a first contact electrode formed on the substrate; a dielectric layer disposed on the substrate and formed with an opening for a layer of the phase-change material to be formed therein; and at least a second contact electrode disposed on the dielectric layer. As the phase-change material is in a single crystalline state and of a great discrepancy between high and low resistance states, the memory unit using the phase-changed material can achieve a phase-change characteristic rapidly by pulse voltage and avert any incomplete reset while with a low critical power.