Diode Or Charge-coupled Device (ccd) (epo) Patents (Class 257/E31.084)
  • Patent number: 11764170
    Abstract: A sensing substrate and an electronic device are provided. The sensing substrate includes a sensing unit on a base substrate. The sensing unit includes a sensing element and a conductive pattern, the sensing element has a light incident surface and a back surface that are opposite and a side surface between the light incident surface and the back surface. The conductive pattern is on a side of the sensing element away from the base substrate, and has a hollow portion and a transparent conductive portion surrounding the hollow portion, an orthographic projection of the hollow portion on the base substrate is at least partially within an orthographic projection of the sensing element on the base substrate, and an orthographic projection of the transparent conductive portion on the base substrate at least partially overlaps with an orthographic projection of the side surface of the sensing element on the base substrate.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: September 19, 2023
    Assignees: BEIJING BOE SENSOR TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guan Zhang, Jianxing Shang, Huinan Xia, Bin Zhao
  • Patent number: 8946795
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8823070
    Abstract: In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ihara Hisanori
  • Patent number: 8753917
    Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
  • Publication number: 20140077057
    Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Calvin Yi-Ping CHAO, Kuo-Yu CHOU, Fu-Lung HSUEH
  • Publication number: 20130285180
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Jui Wang, Szu-Ying Chen, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 8552480
    Abstract: In one embodiment, a detector includes an AlzIn(1-x)Sb passivation/etch stop layer, an AlxIn(1-x)Sb absorber layer disposed above the Alzn(1-z)Sb passivation/etch stop layer, and an AlyIn(1-y)Sb passivation layer disposed above the AlxIn(1-x)Sb absorber layer, wherein x<z and x<y. The detector further includes a junction formed in a region of the AlxIn(1?x)Sb absorber layer, and a metal contact disposed above the junction and through the AlyIn(1-y)Sb passivation layer.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: October 8, 2013
    Assignee: Flir Systems, Inc.
    Inventors: Richard E. Bornfreund, Jeffrey B. Barton
  • Patent number: 8552479
    Abstract: In one embodiment, a detector includes an AlxIn(1-x)Sb absorber layer, and an AlyIn(1-y)Sb passivation layer disposed above the AlxIn(1-x)Sb absorber layer, wherein x<y. The detector further includes a junction formed in a region of the AlxIn(1-x)Sb absorber layer, and a metal contact disposed above the junction and through the AlyIn(1-y)Sb passivation layer.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: October 8, 2013
    Assignee: Flir Systems, Inc.
    Inventors: Richard E. Bornfreund, Jeffrey B. Barton
  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Publication number: 20130075791
    Abstract: In various embodiments, a charge-coupled device includes channel stops laterally spaced away from the channel by fully depleted regions.
    Type: Application
    Filed: September 20, 2012
    Publication date: March 28, 2013
    Inventor: Christopher Parks
  • Publication number: 20130056809
    Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, an imaging pixel of an image sensor includes a photodiode region to accumulate an image charge in response to incident light, a first transistor having a gate oxide layer, the gate oxide layer having a first level of nitridation, and a second transistor having a gate oxide layer, the gate oxide layer having a second level of nitridation that is higher than the first level of nitridation.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Inventors: Duli Mao, Hsin Chih Tai, Vincent Venezia, Howard Rhodes
  • Publication number: 20130056808
    Abstract: An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Inventors: Hsin-Chih Tai, Keh-Chiang Ku, Duli Mao, Vincent Venezia, Gang Chen
  • Publication number: 20130020621
    Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.
    Type: Application
    Filed: September 25, 2012
    Publication date: January 24, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Publication number: 20120301990
    Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.
    Type: Application
    Filed: August 10, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, JR., John J. Ellis-Monaghan, Edward J. Nowak
  • Publication number: 20120280109
    Abstract: Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Keh-Chiang Ku, Rongsheng Yang
  • Publication number: 20120273854
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Application
    Filed: June 30, 2011
    Publication date: November 1, 2012
    Applicant: APTINA IMAGING CORPORATION
    Inventors: Sergey Velichko, Jingyi Bai
  • Publication number: 20120235026
    Abstract: An image sensor pixel and a driving method thereof are provided. The image sensor pixel comprises a photodiode, a sensing capacitor, a static transistor and a dynamic transistor. A first terminal of the photodiode is coupled to a bias line. A control terminal of the static transistor is coupled to a static gate line, and a first terminal of the static transistor is coupled to a first terminal of the sensing capacitor and a second terminal of the photodiode. A control terminal of the dynamic transistor is coupled to a dynamic gate line, and a first terminal of the dynamic transistor is coupled to a second terminal of the sensing capacitor.
    Type: Application
    Filed: September 22, 2011
    Publication date: September 20, 2012
    Applicant: CHIMEI INNOLUX CORPORATION
    Inventor: Chih-Hao WU
  • Patent number: 8264013
    Abstract: A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order to surround two sides of an outer-periphery of the voltage conversion section and also to surround a channel section of the charge transfer device and the light receiving devices and an end portion of the device separation insulating film facing an end face of the light receiving device is arranged inwardly below a control electrode with respect to an end face of the control electrode on the light receiving device side.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: September 11, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomohiko Kawamura
  • Publication number: 20120187462
    Abstract: High optical efficiency CMOS image sensors capable of sustaining pixel sizes less than 1.2 microns are provided. Due to high photodiode fill factors and efficient optical isolation, microlenses are unnecessary. Each sensor includes plural imaging pixels having a photodiode structure on a semiconductor substrate adjacent a light-incident upper surface of the image sensor. An optical isolation grid surrounds each photodiode structure and defines the pixel boundary. The optical isolation grid extends to a depth of at least the thickness of the photodiode structure and prevents incident light from penetrating through the incident pixel to an adjacent pixel. A positive diffusion plug vertically extends through a portion of the photodiode structure. A negative diffusion plug vertically extends into the semiconductor substrate for transferring charge generated in the photodiode to a charge collecting region within the semiconductor substrate.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 26, 2012
    Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon LAW, Dan YANG, Xunqing SHI
  • Publication number: 20120175690
    Abstract: A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.
    Type: Application
    Filed: March 2, 2011
    Publication date: July 12, 2012
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Yue-Ming Hsin, Fang-Ping Chou, Ching-Wen Wang, Guan-Yu Chen
  • Patent number: 8188522
    Abstract: A back-illuminated type solid-state imaging device including (a) a semiconductor layer on a front surface side of a semiconductor substrate with an insulation film between them; (b) a photoelectric conversion element that constitutes a pixel in the semiconductor substrate; (c) at least part of transistors that constitute the pixel in the semiconductor film; and (d) a rear surface electrode to which a voltage is applied on the rear surface side of the semiconductor substrate, wherein, (1) a semiconductor layer of an opposite conduction type to a charge accumulation portion of the photoelectric conversion element is formed in the semiconductor substrate under the insulation film, and (2) the same voltage as the voltage applied to the rear surface electrode is applied to the semiconductor layer.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Publication number: 20120100659
    Abstract: A method for manufacturing a solid-state image sensor includes forming a gate electrode structure including a gate electrode on a gate insulating film formed on a semiconductor substrate, and implanting ions into a first region and simultaneously implanting the ions into a second region of the semiconductor substrate via the gate electrode structure and the gate insulating film, wherein the first region is a region where a charge accumulation region is to be formed, and the second region is a region where an extended region that extends from the charge accumulation region to a portion below the gate electrode is to be formed, and a mean projected range of the ions in the step of simultaneous implanting of the ions into the first region and the second region is larger than a sum total of thicknesses of the gate electrode and the gate insulating film.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 26, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Junji Iwata
  • Patent number: 8163591
    Abstract: A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 24, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Sung-Hyung Park, Ju-Il Lee
  • Patent number: 8120069
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 21, 2012
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 8115242
    Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: February 14, 2012
    Assignee: Foveon, Inc.
    Inventor: Richard B. Merrill
  • Publication number: 20120007149
    Abstract: In a solid-state imaging device 1, an overflow gate (OFG) 5 has a predetermined electric resistance value, while voltage application units 161 to 165 are electrically connected to the OFG 5 at connecting parts 171 to 175. Therefore, when voltage values V1 to V5 applied to the connecting parts 171 to 175 by the voltage application units 161 to 165 are adjusted, the OFG 5 can yield higher and lower voltage values in its earlier and later stage parts, respectively. As a result, the barrier level (potential) becomes lower and higher in the earlier and later stage parts, so that all the electric charges generated in an earlier stage side region of photoelectric conversion units 2 can be caused to flow out to an overflow drain (OFD) 4, whereby only the electric charges generated in a later stage side region of the photoelectric conversion units 2 can be TDI-transferred.
    Type: Application
    Filed: March 25, 2010
    Publication date: January 12, 2012
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hisanori Suzuki, Yasuhito Yoneta, Kentaro Maeta, Masaharu Muramatsu
  • Publication number: 20110278649
    Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.
    Type: Application
    Filed: May 14, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. ANDERSON, Andres BRYANT, William F. CLARK, JR., John J. ELLIS-MONAGHAN, Edward J. NOWAK
  • Publication number: 20110272749
    Abstract: Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 10, 2011
    Inventors: Fumiyasu UTSUNOMIYA, Taro YAMASAKI, Isamu FUJII
  • Publication number: 20110241080
    Abstract: Disclosed herein is a solid-state imaging device, including a plurality of unit pixels, wherein the plurality of unit pixels include: a photoelectric conversion element; a first transfer gate; a charge retaining region; a second transfer gate; and a floating diffusion region; a boundary part between the photoelectric conversion element and the charge retaining region having a structure of an overflow path formed at a potential determining a predetermined amount of charge, the overflow path transferring a charge by which the predetermined amount of charge is exceeded as a signal charge from the photoelectric conversion element to the charge retaining region, and the first transfer gate having two electrodes with different work functions as gate electrodes arranged above the overflow path and above the charge retaining region, respectively.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 6, 2011
    Applicant: SONY CORPORATION
    Inventor: Shinya Yamakawa
  • Publication number: 20110237014
    Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: SONY CORPORATION
    Inventors: Susumu Hiyama, Tomoyuki Hirano
  • Publication number: 20110204425
    Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well.
    Type: Application
    Filed: December 27, 2010
    Publication date: August 25, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: ROGER LEE, Jianping Yang
  • Publication number: 20110207260
    Abstract: It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased.
    Type: Application
    Filed: May 5, 2011
    Publication date: August 25, 2011
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20110187911
    Abstract: A solid-state imaging device is provided, which includes a pixel region in which pixels including a photoelectric conversion section and a plurality of pixel transistors are arranged. In the solid-state imaging device, a transfer transistor of the pixel transistors includes: a transfer gate electrode extended in a surface of the substrate formed on the surface of a semiconductor substrate; and a transfer gate electrode buried in the substrate which is electrically insulated from the transfer gate electrode extended in a surface of the substrate and is embedded in the inside of the semiconductor substrate in the vertical direction through the transfer gate electrode extended in a surface of the substrate.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 4, 2011
    Applicant: SONY CORPORATION
    Inventor: Takekazu Shinohara
  • Publication number: 20110168873
    Abstract: Disclosed are a pinned photodiode having and electrically controllable pinning layer and an image sensor including the pinned photodiode. A predetermined voltage is applied to the pinning layer for the depletion duration of the photodiode in the image sensor, so that stable surface pinning is acquired and the uniform surface pinning is achieved between pixels.
    Type: Application
    Filed: August 19, 2009
    Publication date: July 14, 2011
    Applicant: CROSSTEK CAPITAL, LLC
    Inventor: Man Lyun Ha
  • Publication number: 20110171770
    Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.
    Type: Application
    Filed: March 28, 2011
    Publication date: July 14, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ryuichi Mishima, Mineo Shimotsusa, Hiroaki Naruse
  • Publication number: 20110169993
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Howard E. Rhodes
  • Publication number: 20110156105
    Abstract: A sensor includes a substrate, a floating diffusion node in the substrate, a photodiode in the substrate laterally spaced apart from the floating diffusion region and a transfer transistor coupling the photodiode and the floating diffusion region. The sensor further includes a photodiode control electrode disposed on the photodiode and configured to control a carrier distribution of the photodiode responsive to a control signal applied thereto. The floating diffusion region may have a first conductivity type, the photodiode may include a first semiconductor region of a second conductivity type disposed on a second semiconductor region of the first conductivity type, and the photodiode control electrode may be disposed on the first semiconductor region. The photodiode may be configured to receive incident light from a side of the substrate opposite the photodiode control electrode.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 30, 2011
    Inventors: Yi-tae Kim, Jung-chak Ahn
  • Publication number: 20110156104
    Abstract: A solid-state imaging device including a semiconductor substrate, a photoelectric conversion portion interposed between a lower electrode and an upper electrode, a contact plug formed so as to connect the lower electrode and the semiconductor substrate in order to read signal charges generated in the photoelectric conversion portion to the semiconductor substrate side, a vertical type transmitting path configured by sequentially laminating a connection portion for electrically connecting the contact plug to the semiconductor substrate, a charge accumulation layer for accumulating the signal charges read to the connection portion, and a potential barrier layer configuring a potential barrier between the connection portion and the charge accumulation layer in a vertical direction of the semiconductor substrate, and a charge reading portion configured to read the signal charges accumulated in the charge accumulation layer to the circuit forming surface side of the semiconductor substrate.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 30, 2011
    Applicant: SONY CORPORATION
    Inventor: Tetsuji Yamaguchi
  • Patent number: 7964451
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Publication number: 20110141328
    Abstract: A solid-state image sensor including a plurality of pixels formed on a semiconductor substrate, each pixel comprising a photoelectric conversion element including a charge accumulation region of a first conductivity type, a floating diffusion of the first conductivity type, and a transfer transistor which transfers charge in the charge accumulation region to the floating diffusion, comprises an element isolation region made of an insulator and arranged to isolate adjacent pixels from each other, and an impurity diffusion region of a second conductivity type arranged inside the semiconductor substrate to isolate adjacent pixels from each other, wherein a peak position of an impurity concentration of the impurity diffusion region of one pixel is disposed within a width of the floating diffusion, of the one pixel, along a straight line passing through the photoelectric conversion element, a gate electrode of the transfer transistor, and the floating diffusion which are of the one pixel.
    Type: Application
    Filed: November 18, 2010
    Publication date: June 16, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Junji Iwata
  • Patent number: 7948048
    Abstract: In a semiconductor device 10 including a structure where transfer electrodes 2a to 2c are disposed on a semiconductor substrate 1 via an insulation layer 3, a first semiconductor region 4 of a first conductivity type, a second semiconductor region 5 of a conductivity type opposite to the first conductivity type, and a third semiconductor region 6 of the first conductivity type in a position that overlaps a region of the semiconductor substrate 1 directly underneath the transfer electrodes 2a to 2c. The second semiconductor region 5 is formed on the first semiconductor region 4. The third semiconductor region 6 is formed on the second semiconductor region 5 so that a position of a maximal point 8 of electric potential of the second semiconductor region 5 when being depleted is deeper than a position of the maximal point 8 in a case where the third semiconductor region 6 does not exist.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 24, 2011
    Assignee: Panasonic Corporation
    Inventor: Takao Kuroda
  • Publication number: 20110084317
    Abstract: A back-illuminated type solid-state imaging device including (a) a semiconductor layer on a front surface side of a semiconductor substrate with an insulation film between them; (b) a photoelectric conversion element that constitutes a pixel in the semiconductor substrate; (c) at least part of transistors that constitute the pixel in the semiconductor film; and (d) a rear surface electrode to which a voltage is applied on the rear surface side of the semiconductor substrate, wherein, (1) a semiconductor layer of an opposite conduction type to a charge accumulation portion of the photoelectric conversion element is formed in the semiconductor substrate under the insulation film, and (2) the same voltage as the voltage applied to the rear surface electrode is applied to the semiconductor layer.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 14, 2011
    Applicant: SONY CORPORATION
    Inventor: Keiji Mabuchi
  • Patent number: 7851822
    Abstract: A charge-coupled device includes a photosensitive region for collecting charge in response to incident light; a first and third gate electrode made of a transmissive material spanning at least a portion of the photosensitive region; and a second gate electrode made of a transmissive material that is less transmissive than the first and third gates and spans at least a portion of the photosensitive region; wherein the first, second and third gates are arranged symmetrically within an area that spans the photosensitive region.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: December 14, 2010
    Assignee: Eastman Kodak Company
    Inventor: Eric J. Meisenzahl
  • Patent number: 7847326
    Abstract: A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 7, 2010
    Inventors: Sung-Hyung Park, Ju-Il Lee
  • Patent number: 7838955
    Abstract: An image sensor includes a metal interconnection and readout circuitry over a first substrate, an image sensing device, and an ion implantation isolation layer. The image sensing device is over the metal interconnection, and an ion implantation isolation layer is in the image sensing device. The image sensing device includes first, second and third color image sensing units, and ion implantation contact layers. The first, second and third color image sensing units are stacked in or on a second substrate. The ion implantation contact layers are electrically connected to the first, second and third color image sensing units, respectively.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 23, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hee Sung Shim
  • Patent number: 7834411
    Abstract: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: November 16, 2010
    Assignee: Foveon, Inc.
    Inventors: Richard B. Merrill, Shri Ramaswami, Glenn J. Keller
  • Patent number: 7777259
    Abstract: Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region that is connected to the photodiodes on a side of the n+ wall to receive charges from the photodiodes, wherein a p-type region is formed between the floating diffusion region and the n+ wall, and the plurality of photodiodes have a multi-potential well structure.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Patent number: 7759157
    Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 20, 2010
    Assignee: FujiFilm Corporation
    Inventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
  • Patent number: 7755108
    Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi