For Device Having Potential Or Surface Barrier (epo) Patents (Class 257/E31.12)
  • Patent number: 8916409
    Abstract: An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Hisham S. Mohamed, Devendra K. Sadana
  • Patent number: 8847297
    Abstract: Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, June-Taeg Lee, Jae-Hee Choi
  • Patent number: 8841158
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8623692
    Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Myung Su Kim, Min Chul Song, Soon Young Park, Dong Seop Kim, Sung Chan Park, Yoon Mook Kang, Tae Jun Kim, Min Ki Shin, Sang Won Lee, Heung Kyoon Lim
  • Patent number: 8624344
    Abstract: A solid state imaging device according to an embodiment includes a light sensing part which conducts photoelectric conversion on incident light. The solid state imaging device includes a ferroelectric layer including an organic compound on a surface of the light sensing part on which light is incident. The solid state imaging device includes a transparent electrode formed on the ferroelectric layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Arayashiki, Kazuaki Nakajima
  • Patent number: 8598640
    Abstract: A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventors: Yoshiaki Kitano, Hideshi Abe, Jun Kuroiwa, Kiyoshi Hirata, Hiroaki Ohki, Nobuhiro Karasawa, Ritsuo Takizawa, Mitsuru Yamashita, Mitsuru Sato, Katsunori Kokubun
  • Patent number: 8575661
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8535970
    Abstract: The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ranier Krauser, Lawrence A. Clevenger, Kevin Prettyman, Brian Christopher Sapp, Kevin S. Petrarca, Harold John Hovel, Gerd Pfeiffer, Zhengwen Li, Carl John Radens
  • Patent number: 8508043
    Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8399271
    Abstract: A display apparatus includes a substrate; a first insulating layer formed on the substrate and having an upper surface including a concavo-convex area including one or more concave features and one or more convex features; a first storage electrode overlaying the upper surface and a side surface of the first insulating layer and having an upper surface including a concavo-convex area including one or more concave features and one or more convex features, each concave feature of the first storage electrode overlying at least one respective concave feature of the first insulating layer, each convex feature of the first storage electrode overlying at least one respective convex feature of the first insulating layer; a second insulating layer formed on the first storage electrode; and a second storage electrode formed on the second insulating layer which separates the second storage electrode from the underlying first storage electrode.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae-Jin Park, Kyu-Young Kim, Hyung Il Jeon, Ju-Han Bae
  • Publication number: 20130049022
    Abstract: An optoelectonice device package, an array of optoelectronic device packages and a method of fabricating an optoelectronic device package. The array includes a plurality of optoelectronic device packages, each enclosing an optoelectronic device, and positioned in at least one row. Each package including two geometrically parallel transparent edge portions and two geometrically parallel non-transparent edge portions, oriented substantially orthogonal to the transparent edge portions. The transparent edge portions are configured to overlap at least one adjacent package, and may be hermetically sealed. The optoelectronic device portion fabricated using R2R manufacturing techniques.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventor: Donald Seton Farquhar
  • Publication number: 20130045562
    Abstract: A method of forming a photovoltaic device containing a buried emitter region and vertical metal contacts is provided. The method includes forming a plurality of metal nanoparticles on exposed portions of a single-crystalline silicon substrate that are not covered by patterned antireflective coatings (ARCs). A metal nanoparticle catalyzed etching process is then used to form trenches within the single-crystalline silicon substrate and thereafter the metal nanoparticles are removed from the trenches. An emitter region is then formed within exposed portions of the single-crystalline silicon substrate, and thereafter a metal contact is formed atop the emitter region.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jun Liu, Qiang Huang, Young-Hee Kim
  • Publication number: 20120312367
    Abstract: Discussed is a solar cell including a substrate having a first conductivity type; an emitter layer including a plurality of finger lines connected with an emitter layer; a plurality of rear finger lines connected with a back surface field, wherein the emitter layer includes first areas in contact with the plurality of front finger lines and second areas positioned between the plurality of front finger lines and having a lower doping concentration than that of the first areas, the back surface field includes areas in contact with the plurality of rear finger lines, and the number of the plurality of rear finger lines positioned on a rear surface of the substrate and the number of the plurality of front finger lines positioned on a front surface of the substrate are different.
    Type: Application
    Filed: March 22, 2012
    Publication date: December 13, 2012
    Inventors: Yoonsil JIN, Youngho CHOE
  • Patent number: 8330243
    Abstract: A semiconductor light-detecting element includes: a semiconductor substrate of a first conductivity type having a band gap energy, a first principal surface, and a second principal surface opposed to the first principal surface; a first semiconductor layer of the first conductivity type on the first principal surface and having a band gap energy smaller than the band gap energy of the semiconductor substrate; a second semiconductor layer of the first conductivity type on the first semiconductor layer; an area of a second conductivity type on a part of the second semiconductor layer; a first electrode connected to the second semiconductor layer; a second electrode connected to the area; and a low-reflection film on the second principal surface. The second principal surface is a light-detecting surface detecting incident light, and no substance or structure having a higher reflection factor, with respect to the incident light, than the low-reflection film, is located on the second principal surface.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: December 11, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Matobu Kikuchi
  • Publication number: 20120305066
    Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
  • Publication number: 20120282723
    Abstract: A solid-state imaging device including a light-receiving portion, which serves as a pixel, and a waveguide, which is disposed at a location in accordance with the light-receiving portion and which includes a clad layer and a core layer embedded having a refractive index distribution in the wave-guiding direction.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 8, 2012
    Applicant: SONY CORPORATION
    Inventors: Hiromi Wano, Takamasa Tanikuni, Shinichi Yoshida
  • Publication number: 20120217535
    Abstract: The invention relates to a method of encapsulating a flexible optoelectronic multi-layered structure (6) provided on a polymer substrate (2) comprising the steps of providing the flexible optoelectronic multi-layered structure with one or both a bottom encapsulation stack (B) and a top encapsulation stack (T), wherein the bottom encapsulation stack and the top encapsulation layer comprise a first inorganic layer (4a, 8a) separated from a second inorganic layer (4b, 8b) by a substantially continuous getter layer (5, 8) comprising a metal oxide, the first and the second inorganic layers having an intrinsic water vapour transmission of 10?5 g·m?2·day?1 or less.
    Type: Application
    Filed: July 9, 2010
    Publication date: August 30, 2012
    Applicant: Nederlandse Organisatie voor toegepase- Natuurwetenschappelijk onderzoek TNO
    Inventors: Peter Van de Weijer, Antonius Maria Bernardus Van Mol, Cristina Tanase
  • Publication number: 20120118372
    Abstract: A solar cell includes a substrate of a first conductive type, an emitter layer which is positioned at an incident surface of the substrate and has a second conductive type opposite the first conductive type, a front electrode which is positioned on the incident surface of the substrate and is electrically connected to the emitter layer, a back passivation layer which is positioned on a back surface opposite the incident surface of the substrate, has at least one hole, and contains intrinsic silicon, and a back electrode layer positioned on the back passivation layer. The back electrode layer is electrically connected to the substrate through the at least one hole of the back passivation layer and contains a distribution of a silicon material.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 17, 2012
    Inventors: Daeyong LEE, Junyong Ahn, Jihoon Ko
  • Publication number: 20120104531
    Abstract: Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process.
    Type: Application
    Filed: July 27, 2011
    Publication date: May 3, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Mi-Ran PARK, O-Kyun Kwon
  • Publication number: 20120056290
    Abstract: A method of manufacturing a layer stack adapted for a thin-film solar cell and a precursor for a solar cell are described. The method includes depositing a TCO layer over a transparent substrate, depositing a first conductive-type layer, wherein the depositing includes: providing for a first SiOx-containing anti-reflection layer by chemical vapor deposition. The method further includes depositing a first intrinsic-type layer and depositing a further conductive-type layer with a conductivity opposite to the first conductive-type layer.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 8, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Stefan KLEIN, Konrad SCHWANITZ, Tobias STOLLEY
  • Patent number: 8110885
    Abstract: Provided is a MOS type solid state imaging device, including a semiconductor substrate, a plurality of pixels arranged on the semiconductor substrate, each pixel having a light receiving element for generating a signal charge due to incident light, and a MOS transistor for reading the signal charge, and a hydrogen supply film arranged on the semiconductor substrate over the plurality of pixels and having a region corresponding to the light receiving element at least a part of which has a film thickness greater than the other part of the region.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: February 7, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoko Iida, Takanori Watanabe
  • Patent number: 8101454
    Abstract: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: William J. Baggenstoss
  • Publication number: 20110318865
    Abstract: The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ranier Krauser, Lawrence A. Clevenger, Kevin Prettyman, Brian Christopher Sapp, Kevin S. Petrarca, Harold John Hovel, Gerd Pfeiffer, Zhengwen Li, Carl John Radens
  • Publication number: 20110308602
    Abstract: A solar cell includes a semiconductor substrate and an antireflection layer arranged on the light incidence side on the front-side surface of a semiconductor substrate. The antireflection layer has a limit voltage of less than 10 volts, less than 5 volts, or less than 3 volts, along a layer thickness of the antireflection layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Applicant: Q-CELLS SE
    Inventors: Matthias JUNGHÄNEL, Andreas KUX, Martin SCHÄDEL, Maximilian SCHERFF
  • Publication number: 20110284068
    Abstract: The disclosed subject matter provides a method and structure for obtaining ultra-low surface recombination velocities from highly efficient surface passivation in crystalline silicon substrate-based solar cells by utilizing a bi-layer passivation scheme which also works as an efficient ARC. The bi-layer passivation consists of a first thin layer of wet chemical oxide or a thin hydrogenated amorphous silicon layer. A second layer of amorphous hydrogenated silicon nitride film is deposited on top of the wet chemical oxide or amorphous silicon film. This deposition is then followed by annealing to further enhance the surface passivation.
    Type: Application
    Filed: April 23, 2011
    Publication date: November 24, 2011
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, Anand Deshpande, Rafael Ricolcol, Sean M. Seutter
  • Publication number: 20110279717
    Abstract: Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.
    Type: Application
    Filed: April 14, 2011
    Publication date: November 17, 2011
    Applicant: Sony Corporation
    Inventors: Satoru Wakiyama, Hiroshi Ozaki
  • Publication number: 20110272011
    Abstract: A device, system, and method for a thin Si solar cell with epitaxial lateral overgrowth (ELO) structure described in may demonstrate higher open circuit voltage are disclosed herein. An exemplary thin silicon solar cell structure has a p+ silicon substrate. A dielectric layer is disposed over the p+ silicon substrate. One or more trenches are defined within the dielectric layer. A thin n type silicon layer is grown on the p+ silicon substrate within the trench by epitaxial lateral overgrowth wherein a junction area of the solar cell is minimized.
    Type: Application
    Filed: June 7, 2010
    Publication date: November 10, 2011
    Applicant: AMBERWAVE, INC.
    Inventors: Anthony Lochtefeld, Allen Barnett
  • Publication number: 20110224487
    Abstract: Size reduction of an image pickup module is promoted, and reliability of electric connection and electric noise resistance are improved by decreasing the numbers of components and connection spots. The problems are solved by providing an image pickup module including a solid-state image pickup element chip having an image pickup surface, a cover glass that covers the image pickup surface, and a wiring board on which the solid-state image pickup element chip is mounted, in which the solid-state image pickup element chip and the wiring board have an overlap structure in which end portions thereof are overlapped with each other, and a first electrode portion formed on the end portion of the solid-state image pickup element chip and a second electrode portion formed on the end portion of the wiring board are electrically connected through a bump.
    Type: Application
    Filed: January 25, 2011
    Publication date: September 15, 2011
    Applicant: FUJIFILM CORPORATION
    Inventor: Teppei OGAWA
  • Patent number: 7994600
    Abstract: Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive index layer overlying a reflective surface of an integrated circuit, a first low refractive index layer overlying the first high refractive index layer, a second high refractive index layer overlying the first low refractive index layer, and a second low refractive index layer overlying the second high refractive index layer. The alternating layers of high refractive index material and low refractive index material form an optical trap, allowing light to readily pass through in one direction, but not so easily in a reverse direction. The dual alternating layer topology improves the antireflective properties of the antireflective layer and permits a wide range of adjustments for manipulating reflectivity and color point.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: August 9, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Simon Joshua Jacobs, Duane Scott Dewald, Leigh A. Files, Terry A. Bartlett
  • Publication number: 20110189810
    Abstract: A method of forming a selective emitter in a photovoltaic (PV) crystalline silicon semiconductor wafer involves forming a mask on a front side surface of the wafer to create masked and unmasked areas on the front side surface. A first silicon oxide layer is electrochemically formed at the unmasked areas of the front side surface such that the silicon oxide layer extends into an emitter of the wafer at least as far as a dead zone therein. The mask is removed and the first silicon oxide layer is etched back until substantially all of the first silicon oxide layer is removed. A second silicon oxide layer is then electrochemically formed on the front side surface such that the second silicon oxide layer has sufficient thickness to passivate the front side surface.
    Type: Application
    Filed: July 28, 2008
    Publication date: August 4, 2011
    Applicant: DAY4 ENERGY INC.
    Inventors: Leonid B. Rubin, Bram Sadlik, Alexander Osipov
  • Publication number: 20110177651
    Abstract: A method for producing a metal structure on a surface of a semiconductor substrate, including the following steps: A applying a metal layer, B applying a structuring layer and C removing the structuring layer. Either step B is carried out after step A, and step C after step B in a masking method, so that the structuring layer covers the metal layer at least partially and, after step B is carried out, the metal layer is removed from the regions not covered by the structuring layer, before step C is carried out or, in a lift-off method, step A is carried out after step B, and step C after step A, so that the structuring layer is covered essentially by the metal layer and, at least in the regions, in which the metal layer covers the structuring layer, the metal layer is detached when step C is carried out. It is essential that the structuring layer in step B is produced by a hot melt ink.
    Type: Application
    Filed: June 19, 2009
    Publication date: July 21, 2011
    Applicant: Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.
    Inventors: Nicola Mingirulli, Daniel Biro, Christian Schmiga, Jan Specht, David Stuwe
  • Publication number: 20110155204
    Abstract: Disclosed herein is a wire type thin film solar cell, including: a metal wire which is made of any one selected from the group consisting of aluminum (Al), titanium (Ti), chromium (Cr), molybdenum (Mo) and tungsten (W); an N-type layer which is deposited on a circumference of the metal wire and conducts electrons generated from the metal wire; a P-type layer which is deposited on the N-type layer and emits electrons excited by solar light; and a transparent electrode layer which is deposited on the P-type layer. The wire type thin film solar cell can exhibit high photoelectric conversion efficiency compared to conventional flat-plate type thin film solar cells and can be easily manufactured into a highly-dense solar cell module.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 30, 2011
    Inventors: Jun Sin Yi, Jin Joo Park, Young Kuk Kim
  • Publication number: 20110139248
    Abstract: Solar cells, methods for manufacturing a quantum dot layer for a solar cell, and methods for manufacturing solar cells are disclosed. An example method for manufacturing a quantum dot layer for a solar cell includes providing an electron conductor layer, providing a quantum dot chemical bath deposition solution, controlling the temperature of the quantum dot chemical bath deposition solution to a temperature of about 30° C. or greater, and immersing the electron conductor layer in the quantum dot chemical bath deposition solution for about 1-10 hours. The quantum dot chemical bath deposition solution may include CdSe.
    Type: Application
    Filed: January 20, 2010
    Publication date: June 16, 2011
    Applicant: Honeywell International Inc.
    Inventors: Anna Liu, Zhi Zheng, Linan Zhao, Marilyn Wang
  • Publication number: 20110094573
    Abstract: A solar cell and a method for fabricating the same are provided. The solar cell includes a first electrode, a second electrode, a photoelectric conversion layer and a non-conductive reflector. The first electrode including a nano-metal transparent conductive layer is disposed on a transparent substrate. The nano-metal transparent conductive layer substantially contacts with the photoelectric conversion layer. The second electrode is disposed between the photoelectric conversion layer and the transparent substrate. The photoelectric conversion layer is disposed between the first and the second electrodes. The non-conductive reflector is disposed on the first electrode.
    Type: Application
    Filed: December 15, 2009
    Publication date: April 28, 2011
    Applicant: Industrial Technology Research Institute
    Inventors: Chien-Liang Wu, Jun-Chin Liu, Ming-Jyh Chang, Hsing-Hua Wu, Yu-Ming Wang
  • Publication number: 20110083735
    Abstract: A solar cell and a fabricating method thereof are provided. In the method of fabricating the solar cell, a p-type semiconductor substrate on whose light-receiving surface an anti-reflection coating is formed is loaded into a processing chamber. In this case, the p-type semiconductor substrate may be loaded on a substrate support of an apparatus of processing a plurality of substrates along the circumference of the substrate support, in the state where the back surface of the p-type semiconductor substrate faces upward. Then, a back surface field (BSF) layer having the characteristic of Negative Fixed Charge (NFC) is formed with AlO, AlN or ALON on the back surface of the p-type semiconductor substrate.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: IPS Ltd.
    Inventors: Sang-Joon Park, Seong-Beom Park, Young-Jun Kim, Jun-Sung Bae
  • Publication number: 20110073176
    Abstract: A solar cell includes a semiconductor substrate including; a p-type layer, and an n-type layer disposed adjacent to the p-type layer, a dielectric layer positioned on one surface of the semiconductor substrate, a protective layer positioned on one surface of the dielectric layer, a first electrode electrically connected to the p-type layer of the semiconductor substrate and a second electrode electrically connected to the n-type layer of the semiconductor substrate.
    Type: Application
    Filed: March 8, 2010
    Publication date: March 31, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Jong KIM
  • Publication number: 20110056549
    Abstract: In a thin-film solar module comprising a transparent substrate (1), a transparent doped zinc oxide front electrode film (2) deposited on substrate (1), a semiconductor film (3), an optional doped zinc oxide rear electrode film (4), and a reflecting layer (5) on the rear surface turned away from the side of light incidence (hv), the dopant quantities in doped zinc oxide front and/or rear electrode films (2, 4) decrease from substrate (1) towards semiconductor film (3) and from semiconductor film (3) towards reflecting layer (5), respectively.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 10, 2011
    Inventors: Michael Berginski, Peter Lechner
  • Publication number: 20110048524
    Abstract: A thin film solar cell, includes: a first electrode; a light absorption layer including a first light absorption layer including a group I element-group III element-group VI element compound, a second light absorption layer including a group I element-group III element-group VI element compound, and a third light absorption layer including a group I element-group III element-group VI element compound; and a second electrode, wherein the first light absorption layer has a band gap, which is less a band gap of the second light absorption layer, the band gap of the second light absorption layer is less than a band gap of the third light absorption layer, and the second light absorption layer has a band gap gradient, which increases in a direction from the first light absorption layer to the third light absorption layer.
    Type: Application
    Filed: January 22, 2010
    Publication date: March 3, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gyu NAM, Sang-Cheol PARK, Jin-Soo MUN, Yu-Hee KIM, Ji-Beom YOO
  • Publication number: 20110011447
    Abstract: A method of forming a ceramic silicon oxide type coating and a method of producing an inorganic base material having this coating, by coating an organohydrogensiloxane/hydrogensiloxane copolymer on the surface of an inorganic base material and converting the coating into a ceramic silicon oxide type coating by heating to high temperatures in an inert gas or an oxygen-containing inert gas (oxygen gas less than 20 volume %). A coating-forming agent comprising an organohydrogensiloxane/hydrogensiloxane copolymer or its solution. A semiconductor device comprising at least a semiconductor layer formed on a silicon oxide type coating on an inorganic substrate.
    Type: Application
    Filed: October 3, 2008
    Publication date: January 20, 2011
    Inventors: Yukinari Harimoto, Tetsuyuki Michino, Dimitris Elias Katsoulis, Nobuo Kushibiki, Michitaka Suto
  • Publication number: 20100307578
    Abstract: A solar battery module comprises a substrate over a surface of which a solar battery unit is formed, and a resin structure which contacts the substrate and which covers a part of a side surface and a back surface of the substrate. The resin structure comprises a resin and a buffer material having a lower thermal expansion coefficient than the resin, and a mixture ratio of the buffer material with respect to the resin is reduced as a distance from the substrate is increased.
    Type: Application
    Filed: March 12, 2010
    Publication date: December 9, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takeyuki Sekimoto, Toshio Yagiura
  • Publication number: 20100301437
    Abstract: A sensor for capturing light at the ultraviolet (UV) or the deep UV wavelength includes a multi-layer anti-reflective coating (ARC). In a two-layer ARC, the first layer is formed on either the substrate or the circuitry layer, and the second layer is formed on the first layer and receives the light as an incident light beam. Notably, the first layer is at least twice as thick as the second layer, thereby minimizing an electrical field at a substrate surface due to charge trapping in the ARC. In a four-layer ARC, the third layer is formed on the second layer and the fourth layer is formed on the third layer. The first and third layers may be formed from the same material, and the second and fourth layers may be formed from materials having same/similar indexes of refraction. In this case, the first layer is at least twice as thick as any of the second, third, or fourth layers.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Applicant: KLA-Tencor Corporation
    Inventor: David L. Brown
  • Publication number: 20100288356
    Abstract: Disclosed herein are photoactive compositions that include a semiconductor and plasmon-resonating nanoparticles that are capable of concentrating light at a wavelength that is substantially the same as the wavelength of light necessary to promote an electron from a valance band to a conduction band in the semiconductor. As such, the plasmon-resonating nanoparticles direct light to the band gap of the semiconductor at an increased intensity (relative to when such nanoparticles are not present). And because of that increased intensity, the photoactive composition can be more efficiently used to catalyze a photochemical reaction or generate electrical potential in a photovoltaic cell.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 18, 2010
    Applicant: The Regents of the University of Michigan
    Inventors: Suljo Linic, Phillip N. Christopher, David B. Ingram
  • Patent number: 7833812
    Abstract: An optical device comprising an anode, a cathode, an organic semiconducting material between the anode and the cathode, and an electron transport layer between the cathode and the organic semiconducting material wherein the organic semiconducting material comprises sulfur and the electron transport layer containing barium.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: November 16, 2010
    Assignee: Cambridge Display Technology Limited
    Inventor: Salvatore Cina
  • Patent number: 7834411
    Abstract: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: November 16, 2010
    Assignee: Foveon, Inc.
    Inventors: Richard B. Merrill, Shri Ramaswami, Glenn J. Keller
  • Publication number: 20100264505
    Abstract: The present invention is directed toward a dual junction photodiode semiconductor device. The photodiode has a semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type shallowly diffused on the front side of the semiconductor substrate, a second impurity region of the second conductivity type shallowly diffused on the back side of the semiconductor substrate, a first PN junction formed between the first impurity region and the semiconductor substrate, and a second PN junction formed between the second impurity region and the semiconductor substrate. Since light beams of a shorter wavelength are absorbed near the surface of a semiconductor, while light beams of a longer wavelength reach deeper sections, the two PN junctions at front and back sides of the photodiode allow the device to be used as an adjustable low pass or high pass wavelength filter detector.
    Type: Application
    Filed: March 12, 2010
    Publication date: October 21, 2010
    Inventors: Peter Steven Bui, Narayan Dass Taneja, Manoocher Mansouri Aliabadi
  • Publication number: 20100236619
    Abstract: The present invention provides a light transmission type solar cell excellent in both power generation efficiency and light transparency, and also provides a method for producing that solar cell. The solar cell of the present invention comprises a photoelectric conversion layer, a light-incident side electrode layer, and a counter electrode layer. The incident side electrode layer is provided with plural openings bored through the layer, and has a thickness of 10 nm to 200 nm. Each of the openings occupies an area of 80 nm2 to 0.8 ?m2, and the opening ratio is in the range of 10% to 66%. The transmittance of the whole cell is 5% or more at 700 nm wavelength. The incident side electrode layer can be formed by etching fabrication with a stamper. In the etching fabrication, a mono-particle layer of fine particles or a dot pattern formed by self-assembled block copolymer can be used as a mask.
    Type: Application
    Filed: February 4, 2010
    Publication date: September 23, 2010
    Applicant: KABUSHI KAISHA TOSHIBA
    Inventors: Eishi TSUTSUMI, Kumi Masunaga, Ryota Kitagawa, Tsutomu Nakanishi, Akira Fujimoto, Hideyuki Nishizawa, Koji Asakawa
  • Publication number: 20100212733
    Abstract: A solar cell includes a substrate, a protective layer located over a first surface of the substrate, a first electrode located over a second surface of the substrate, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode over the n-type semiconductor layer. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material, and the second electrode is transparent and electrically conductive. The protective layer has an emissivity greater than 0.25 at a wavelength of 2 ?m, has a reactivity with a selenium-containing gas lower than that of the substrate, and may differ from the first electrode in at least one of composition, thickness, density, emissivity, conductivity or stress state. The emissivity profile of the protective layer may be uniform or non-uniform.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Inventors: Chris Schmidt, John Corson
  • Publication number: 20100213564
    Abstract: A sensor chip includes: a semiconductor substrate that is provided with a light receiving portion on a main surface; a light transmissive member that is provided on the main surface of the semiconductor substrate, enclosing a hollow portion above the light receiving portion, to surround upper and periphery of the light receiving portion; and a light transmissive protective member that is provided on the light transmissive member.
    Type: Application
    Filed: September 10, 2009
    Publication date: August 26, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Hideo Numata, Eiji Takano
  • Publication number: 20100206367
    Abstract: A method for fabricating a silicon nano wire, a solar cell including the silicon nano wire and a method for fabricating the solar cell. The solar cell includes a substrate, a first++-type poly-Si layer formed on the substrate, a first-type silicon nano wire layer including a first-type silicon nano wire grown from the first++-type poly-Si layer, an intrinsic layer formed on the substrate having the first-type silicon nano wire layer, and a second-type doping layer formed on the intrinsic layer.
    Type: Application
    Filed: October 23, 2009
    Publication date: August 19, 2010
    Applicant: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Chaehwan JEONG, Minsung JEON, Jin Hyeok KIM, Hang Ju KO, Suk Ho LEE
  • Publication number: 20100193027
    Abstract: A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type, an anti-reflection layer that is positioned on the substrate and is formed of a transparent conductive oxide material, a plurality of emitter layers on the substrate, the plurality of emitter layers being of a second conductive type opposite the first conductive type, a plurality of first electrodes on the plurality of emitter layers, and a plurality of second electrodes that are electrically connected to the substrate and are positioned to be spaced apart from the plurality of first electrodes. The first electrodes and the second electrodes are positioned on the same surface of the substrate.
    Type: Application
    Filed: February 4, 2010
    Publication date: August 5, 2010
    Inventors: Kwangsun JI, Heonmin Lee, Junghoon Choi, Sehwon Ahn