Coatings (epo) Patents (Class 257/E31.119)
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 9029970
    Abstract: Provided is a semiconductor light receiving device including: a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and including an upper surface portion; a reflecting film formed to cover the upper surface portion of the semiconductor layer and including a principal reflecting region and an upper surface; and an upper electrode formed to cover at least one portion of the upper surface of the reflecting film, and including a junction portion extending through the reflecting file to be provided in contact with the upper surface portion of the semiconductor layer, the junction portion of the upper electrode surrounding a portion of a circumference of the principal reflecting region of the reflecting film, the principal reflecting region being connected to a region of the reflecting film located outside the junction portion, in which the semiconductor light receiving device detects light entering from another side of the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 12, 2015
    Assignee: Oclaro Japan, Inc.
    Inventors: Ryu Washino, Yasushi Sakuma, Hiroshi Hamada
  • Patent number: 8969122
    Abstract: Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
  • Patent number: 8952335
    Abstract: Bias lines are provided for respective columns of pixels, and of a plurality of bias lines, bias lines provided at an interval of 10 mm are connected to a bias power source through a current detector. The remaining bias lines are connected directly to the bias power source without passing through the current detector. In each pixel, if electric charge is generated by a radiation detection element in accordance with the dose of irradiated radiation, a current flows in the bias line in accordance with the generated electric charge. The current detector detects the current flowing in the bias line, and a control unit detects, as the timing of starting irradiation of a radiation, when the detected current (current value) is equal to or greater than a threshold value, and starts radiographing of a radiological image.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 10, 2015
    Assignee: Fujifilm Corporation
    Inventor: Keiichiro Sato
  • Patent number: 8933526
    Abstract: An article including a nanostructured functional coating disposed on a substrate is described. The functional coating is characterized by both anti-reflection properties and down-converting properties. Related optoelectronic devices are also described.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: January 13, 2015
    Assignee: First Solar, Inc.
    Inventors: Loucas Tsakalakos, Eric Gardner Butterfield, Alok Mani Srivastava, Bastiaan Arie Korevaar
  • Patent number: 8927434
    Abstract: A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 6, 2015
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
  • Patent number: 8916916
    Abstract: A solid-state imaging device includes: a substrate which is formed of a semiconductor and includes a first surface and a second surface which face opposite sides; a gate insulation film which is formed on a trench formed in the substrate to penetrate the first surface and the second surface; and a gate electrode which is embedded in the trench through the gate insulation film to be exposed to a second surface side of the substrate. A step difference is formed from the second surface of the substrate to a tip end surface of the gate electrode on the second surface side.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: December 23, 2014
    Assignee: Sony Corporation
    Inventor: Hideaki Togashi
  • Patent number: 8916768
    Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 23, 2014
    Assignees: Rec Solar Pte. Ltd., Universitetet I Oslo, Instititt for Energiteknikk
    Inventors: Alexander Ulyashin, Andreas Bentzen, Bengt Svensson, Arve Holt, Erik Sauar
  • Patent number: 8912617
    Abstract: A semiconductor light detection device fabrication technique is provided in which the cap etch and anti-reflection coating steps are performed in a single, self-aligned lithography module.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: December 16, 2014
    Assignee: Solar Junction Corporation
    Inventors: Lan Zhang, Ewelina N. Lucow, Onur Fidaner, Michael W. Wiemer
  • Patent number: 8912579
    Abstract: A solid-state image pickup device includes: a photoelectric conversion portion formed on a substrate and composed of a photodiode; an image pickup area in which plural pixels each including a reading-out electrode for reading out signal electric charges generated and accumulated in the photoelectric conversion portion are formed; and a light blocking film having an opening portion right above the photoelectric conversion portion in an effective pixel area of the image pickup area, and light-blocking said photoelectric conversion portion in an OB pixel area of the image pickup area, in which a film deposited between the light blocking film and the substrate right above the photoelectric conversion portion in the OB pixel area is composed of only a silicon oxide film.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 16, 2014
    Assignee: Sony Corporation
    Inventor: Kaori Takimoto
  • Patent number: 8871557
    Abstract: Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 28, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon Sung Lee, Yong Sun Yoon
  • Patent number: 8796695
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 5, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8791023
    Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 29, 2014
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
  • Patent number: 8790947
    Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colby G. Rampley, Frank T. Laver, Thomas E. Wood
  • Patent number: 8766280
    Abstract: This substrate (11) for a device (50) that collects or emits radiation comprises a transparent polymer layer (1) and a barrier layer (2) on at least one face (1A) of the polymer layer. The barrier layer (2) consists of an antireflection multilayer of at least two thin transparent layers (21, 22, 23, 24) having both alternately lower and higher refractive indices and alternately lower and higher densities, wherein each thin layer (21, 22, 23, 24) of the constituent multilayer of the barrier layer (2) is an oxide, nitride or oxynitride layer.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: July 1, 2014
    Assignee: Saint-Gobain Performance Plastics Corporation
    Inventors: Claire Thoumazet, Emmanuel Valentin, Stephanie Roche
  • Patent number: 8749009
    Abstract: Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 10, 2014
    Assignee: Innova Dynamics, Inc.
    Inventors: Michael Eugene Young, Arjun Daniel Srinivas, Matthew R. Robinson, Alexander Chow Mittal
  • Patent number: 8729654
    Abstract: This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: May 20, 2014
    Assignee: The Regents of the University of California
    Inventors: Woon-Seng Choong, Stephen E. Holland
  • Patent number: 8728851
    Abstract: A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: May 20, 2014
    Assignee: Big Sun Energy Technology Inc.
    Inventors: Sheng Yung Liu, Chin-Tien Yang, Chun-Hung Lin
  • Patent number: 8716054
    Abstract: A method for fabricating an image sensor having a pixel region and a logic region, which includes one of: (1) forming a photodiode in a substrate at the pixel region, (2) forming a first interlayer insulating layer on the substrate, (3) forming a first stop film on the first interlayer insulating layer, (4) forming an insulating film on the first stop film, (5) forming a second stop film on the insulating film, (6) forming at least one trench by selective etching of the second stop film and the insulating film positioned at the pixel region for exposing the first stop film, (7) forming conductive material on the second stop film to fill the at least one trench, and (8) forming a zero wiring layer in the at least one trench by planarizing the conductive material until the second stop film is exposed.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 6, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seong Hun Jeong
  • Publication number: 20140117485
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Publication number: 20140110805
    Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventor: THORALF KAUTZSCH
  • Patent number: 8679889
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 25, 2014
    Assignee: SunPower Corporation
    Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
  • Publication number: 20140061738
    Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung Chien Wang, Yeur-Luen Tu, Cheng-Ta Wu, Jiech-Fun Lu, Chun-Wei Chang, Wang-Pen Mo, Jhy-Jyi Sze, Chia-Shiung Tsai
  • Patent number: 8658888
    Abstract: A solar energy utilization device wherein the surface of the incident light side of the transparent base material 1 is covered by water-and-oil-shedding transparent fine particles 5 being bound and fixed to the surface. A method for manufacturing a solar energy utilization device comprising process A of manufacturing reactive transparent fine particles 9 with the first functional group at one end; process B of manufacturing reactive transparent base material 4 with the second functional group at one end forming a covalent bond with the first functional group; process C of manufacturing transparent base material 10 by reacting the reactive transparent fine particles 9 with the reactive transparent base material 4 for binding and fixing the reactive transparent fine particles 9 to the surface; and process D of forming water-and-oil-shedding coating 16 on the surface of the transparent fine particles 5 being bound and fixed to the surface of the transparent base material 10.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Kazufumi Ogawa
  • Publication number: 20140051202
    Abstract: A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Inventors: Wei-Lin Chen, Chih-Chung Wang, Chiu-Te Lee, Ke-Feng Lin
  • Patent number: 8647914
    Abstract: A method of fabricating a solar cell includes forming an emitter layer of a second conductive type on a front surface and a back surface of a substrate of a first conductive type opposite to the second conductive type, forming an anti-reflection layer on the front surface of the substrate, partially removing the anti-reflection layer and the emitter layer to form an isolation groove dividing the emitter layer into a plurality of regions, removing a portion of the emitter layer formed on the back surface of the substrate, and forming a passivation layer covering the isolation groove and the back surface of the substrate.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 11, 2014
    Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Kyoung-Jin Seo, Yoon-Mook Kang, Min-Chul Song, Dong-Chul Suh, Ju-Hee Song
  • Publication number: 20140035078
    Abstract: The present invention provides a substrate connection type module structure comprising a substrate with a through hole structure and a first contact pad. A chip is configured on the through hole structure of the substrate, with a second contact pad and a sensing area. The first contact pad is coupled to the second contact pad via a wire. A second substrate is electrically connected to the first substrate. The second substrate and the chip are located at the same layer. A lens holder is disposed on the substrate, and a lens is located on the top of the lens holder. A transparent material is disposed within the lens holder. The lens is substantially aligning to the transparent material and the sensing area.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: LARVIEW TECHNOLOGIES CORPORATION
    Inventor: Shin-Dar Jan
  • Publication number: 20140035083
    Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.
    Type: Application
    Filed: November 7, 2012
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsun Wan, Yi-Shin Chu, Szu-Ying Chen, Pao-Tung Chen, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 8637765
    Abstract: Provided is a single junction type CIGS thin film solar cell, which includes a CIGS light absorption layer manufactured using a single junction. The single junction type CIGS thin film solar cell includes a substrate, a back contact deposited on the substrate, a light absorption layer deposited on the back contact and including a P type CIGS layer and an N type CIGS layer coupled to the P type CIGS layer using a single junction, and a reflection prevention film deposited on the light absorption layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: January 28, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Duck Chung, Won Seok Han
  • Patent number: 8637951
    Abstract: A semiconductor light receiving element comprises: a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a non-doped semiconductor light absorbing layer formed on the semiconductor layer of the first conductivity type, a semiconductor layer of a second conductivity type formed on the non-doped semiconductor light absorbing layer, and an electro-conductive layer formed on the semiconductor layer of the second conductivity type. A plurality of openings, periodically arrayed, are formed in a laminated body composed of the electro-conductive layer, the semiconductor layer of the second conductivity type, and the non-doped semiconductor light absorbing layer. The widths of the openings are less than or equal to the wavelength of incident light, and the openings pass through the electro-conductive layer and the semiconductor layer of the second conductivity type to reach the non-doped semiconductor light absorbing layer.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: January 28, 2014
    Assignee: NEC Corporation
    Inventors: Daisuke Okamoto, Junichi Fujikata, Kenichi Nishi
  • Patent number: 8637948
    Abstract: A photovoltaic device including a semiconductor substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first passivation layer on the first surface; and a second passivation layer on the second surface, wherein each of the first passivation layer and the second passivation layer comprises an aluminum-based compound, is disclosed. A method of preparing a photovoltaic device, the method including: forming a semiconductor substrate to have a first surface and a second surface, the second surface being opposite to the first surface; forming an emitter region and a back surface field (BSF) region at the second surface; and forming a first passivation layer on the first surface and a second passivation layer on the second surface, wherein the first passivation layer and the second passivation layer are formed concurrently, is also disclosed.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Hyun-Jong Kim, Czang-Ho Lee, Min Park, Kyoung-Jin Seo, Sang-Won Lee, Jun-Ki Hong, Byoung-Gook Jeong
  • Patent number: 8633558
    Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 21, 2014
    Inventors: Ta-Hsuan Lin, Chuan-Jin Shiu, Chia-Ming Cheng, Tsang-Yu Liu
  • Patent number: 8623692
    Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Myung Su Kim, Min Chul Song, Soon Young Park, Dong Seop Kim, Sung Chan Park, Yoon Mook Kang, Tae Jun Kim, Min Ki Shin, Sang Won Lee, Heung Kyoon Lim
  • Publication number: 20130341746
    Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
    Type: Application
    Filed: July 24, 2012
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-Fann Ting, Yen-Ting Chiang, Ching-Chun Wang
  • Patent number: 8592245
    Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 26, 2013
    Assignee: SRI International
    Inventor: James Robert Janesick
  • Publication number: 20130299886
    Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: November 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • Patent number: 8541860
    Abstract: Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive index layer overlying a reflective surface of an integrated circuit, a first low refractive index layer overlying the first high refractive index layer, a second high refractive index layer overlying the first low refractive index layer, and a second low refractive index layer overlying the second high refractive index layer. The alternating layers of high refractive index material and low refractive index material form an optical trap, allowing light to readily pass through in one direction, but not so easily in a reverse direction. The dual alternating layer topology improves the antireflective properties of the antireflective layer and permits a wide range of adjustments for manipulating reflectivity and color point.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 24, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Simon Joshua Jacobs, Duane Scott Dewald, Leigh A. Files, Terry A. Bartlett
  • Patent number: 8530945
    Abstract: A solid-state image pickup element includes: a photoelectric conversion region formed in a semiconductor substrate; an electric charge holding region formed in the semiconductor substrate for holding electric charges accumulated in the photoelectric conversion region until the electric charges are read out; a transfer gate formed on the semiconductor substrate for transferring electric charges generated by photoelectric conversion in the photoelectric conversion region to the electric charge holding region, and a light blocking film formed on an upper surface of the transfer gate. In this case, a portion between the semiconductor substrate and the light blocking film is thinly formed as a light made incident to the photoelectric conversion region has a longer wavelength in a wavelength region.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 10, 2013
    Assignee: Sony Corporation
    Inventors: Taketo Fukuro, Jun Okuno
  • Publication number: 20130214373
    Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
    Type: Application
    Filed: January 5, 2012
    Publication date: August 22, 2013
    Inventors: Jeffrey W. SCOTT, Colin E. Jones, Ernie J. Caine, Charles A. Cockrum
  • Publication number: 20130193540
    Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
    Type: Application
    Filed: March 30, 2012
    Publication date: August 1, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
  • Publication number: 20130180580
    Abstract: Certain example embodiments of this invention relate to photovoltaic modules that include high contact angle coatings on one or more outermost major surfaces thereof, and/or associated methods. In certain example embodiments, the high contact angle coatings advantageously reduce the likelihood of electrical losses through parasitic leakage of the electrical current caused by moisture on surfaces of the photovoltaic modules, thereby potentially improving the efficiency of the photovoltaic devices. In certain example embodiments, the high contact angle coatings may be nitrides and/or oxides of or including Si, Ti, Ta, TaCr, NiCr, and/or Cr; hydrophobic DLC; and/or polymer-based coatings. The photovoltaic modules may be substrate-type modules or superstrate-type modules in different example embodiments.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicants: C.R.V.C.
    Inventors: Alexey KRASNOV, Jochen Butz, Uwe Kriltz
  • Publication number: 20130164879
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
  • Patent number: 8471300
    Abstract: An image sensor device includes a substrate including a light sensing region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent to the reflective structure. A microlens is provided on a second surface of the substrate opposite the first surface. The microlens is configured to direct incident light to the light sensing region, and the reflective structure is configured to reflect portions of the incident light that pass through the light sensing region back toward the light sensing region. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-Jun Park
  • Publication number: 20130133731
    Abstract: Methods for forming a resistive transparent buffer layer on a substrate are provided. The method can include depositing a resistive transparent buffer layer on a transparent conductive oxide layer on a substrate. The resistive transparent buffer layer can comprise a cadmium doped tin oxide that has an as-deposited stoichiometry where cadmium is present in an atomic amount that is less than 33% of a total atomic amount of tin and cadmium. Zinc may also be provided in the resistive transparent buffer layer in certain embodiments. Additionally, thin film photovoltaic devices having such resistive transparent buffer layers are provided.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Scott Daniel Feldman-Peabody, Robert Dwayne Gossman, George Theodore Dalakos, Anping Zhang, Allan Robert Northrup, Hong Piao, Laurie Le Tarte
  • Patent number: 8445312
    Abstract: A method of manufacturing a crystalline silicon solar cell, subsequently including: providing a crystalline silicon substrate having a first side and a second side opposite the first side; pre-diffusing Phosphorus into a first side of the substrate to render a Phosphorus diffused layer having an initial depth; blocking the first side of the substrate; exposing a second side of the substrate to a Boron diffusion source; heating the substrate for a certain period of time and to a certain temperature so as to diffuse Boron into the second side of the substrate and to simultaneously diffuse the Phosphorus further into the substrate.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 21, 2013
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Valentin Dan Mihailetchi, Yuji Komatsu
  • Publication number: 20130113065
    Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Yin Qian, Hsin-Chih Tai, Keh-Chiang Ku, Vincent Venezia, Duli Mao, Wei Zheng, Howard E. Rhodes
  • Publication number: 20130115732
    Abstract: Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: International Business Machines Corporation
    Inventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang
  • Publication number: 20130112252
    Abstract: A solar cell including a first conductive type semiconductor substrate; a first conductive type first semiconductor layer on a back surface of the semiconductor substrate; a second conductive type second semiconductor layer on the back surface of the semiconductor substrate at a height different from the first semiconductor layer, the second semiconductor layer being separated from the first semiconductor layer; and a passivation layer on the back surface of the semiconductor substrate. The passivation layer covers at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer. The passivation layer includes impurities.
    Type: Application
    Filed: June 20, 2012
    Publication date: May 9, 2013
    Inventors: Kyoung-Jin Seo, Czang-Ho Lee, Hyun-Jong Kim, Min Park, Jun-Ki Hong, Byong-Gook Jeong
  • Publication number: 20130105928
    Abstract: A structure and method of manufacture is disclosed for a backside thinned imager that incorporates a conformal, Al2O3, low thermal budget, surface passivation. This passivation approach facilitates fabrication of backside thinned, backside illuminated, silicon image sensors with thick silicon absorber layer patterned with vertical trenches that are formed by etching the exposed back surface of a backside-thinned image sensor to control photo-carrier diffusion and optical crosstalk. A method of manufacture employing conformal, Al2O3, surface passivation approach is shown to provide high quantum efficiency and low dark current while meeting the thermal budget constraints of a finished standard foundry-produced CMOS imager.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 2, 2013
    Applicant: INTEVAC, INC.
    Inventors: Kenneth A. COSTELLO, Edward YIN, Michael Wayne PELCZYNSKI, Verle W. AEBI
  • Patent number: RE45084
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: August 19, 2014
    Assignee: National Security Agency
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst