Abstract: A method of manufacturing a semiconductor device, includes forming a trench in a semiconductor substrate having a first face and a second face by processing the first face of the semiconductor substrate, the trench including a first portion and a second portion located between the first portion and a plane including a first face, filling an insulator in the second portion such that a space remains in the first portion and the trench is closed, and forming a plurality of elements between the first face and the second face, wherein the space and the insulator form element isolation.

Abstract: Methods are provided herein for deposition of oxide films. Oxide films may be deposited, including selective deposition of oxide thin films on a first surface of a substrate relative to a second, different surface of the same substrate. For example, an oxide thin film such as an insulating metal oxide thin film may be selectively deposited on a first surface of a substrate relative to a second, different surface of the same substrate. The second, different surface may be an organic passivation layer.

Abstract: Provided is an LED display unit group, comprising: an insulation substrate, a front circuit board, and a back circuit board. The front circuit board is divided into pixel areas arranged in an array of 2m rows and 2n columns. Each pixel area comprises three A-electrode pads, three LED light-emitting chips of different light emission colors, and B-electrode pads corresponding to the three LED light-emitting chips. In each pixel area, the electrode A of each LED light-emitting chip is electrically connected to a corresponding A-electrode pad, and the electrode B of each LED light-emitting chip is electrically connected to a corresponding B-electrode pad. In the same column of pixel areas, B-electrode pads corresponding to all LED light-emitting chips are electrically connected to each other. In the same row of pixel areas, A-electrode pads corresponding to LED light-emitting chips of the same light emission color are electrically connected to each other.

Abstract: Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer.

Abstract: A composite pane and in particular to a composite vehicle pane with an integrated light sensor, includes an outer pane and an inner pane that are joined to one another via at least one thermoplastic intermediate layer, and at least one light sensor with a light-sensitive surface that is arranged between the outer pane and the inner pane, wherein the light-sensitive surface faces the outer pane, and a shadow mask that covers at least some portions of the light-sensitive surface is arranged between the light-sensitive surface and the outer pane.

Abstract: Wire-based metallization and stringing techniques for solar cells, and the resulting solar cells, modules, and equipment, are described. In an example, a string of solar cells includes a plurality of back-contact solar cells, wherein each of the plurality of back-contact solar cells includes P-type and N-type doped diffusion regions. A plurality of conductive wires is disposed over a back surface of each of the plurality of solar cells, wherein each of the plurality of conductive wires is substantially parallel to the P-type and N-type doped diffusion regions of each of the plurality of solar cells. One or more of the plurality of conductive wires adjoins a pair of adjacent solar cells of the plurality of solar cells and has a relief feature between the pair of adjacent solar cells.

Abstract: A photovoltaic module for a satellite solar generator, and a flexible satellite solar generator are disclosed including a module having a printed circuit board comprising a substrate made of an insulating material and conductive traces, at least two chains of photovoltaic cells mounted on the face of the substrate supporting the electrically conductive traces and which are connected to the traces such that the traces establish an electrical connection between the chains of cells, and a protective layer that is optically transparent within a range of wavelengths corresponding to the cells' range of photovoltaic conversion, the layer being attached to the printed circuit board so as to cover at least all of the photovoltaic cells and all of the electrically conductive traces of the printed circuit board.

Abstract: The present invention provides a photodiode and a display screen. The photodiode includes a first electrode and a second electrode in order. When a direction of an incident light of the photodiode is a first direction, a material of the first electrode is a transparent conductive material, and a material of the second electrode is a metal material. When the direction of the incident light of the photodiode is a second direction, the second electrode is made of a transparent conductive material, and the first electrode is made of a metal material.

Abstract: A photoelectric conversion device includes a photoelectric conversion region, a readout circuit, and a counting circuit. The photoelectric conversion region is configured to generate a signal charge. The readout circuit is configured to, when reading out a signal that is based on the signal charge generated at the photoelectric conversion region, selectively perform first readout for reading out the signal using avalanche multiplication that is based on the signal charge and second readout for reading out the signal without causing avalanche multiplication to occur with respect to at least a part of the signal charge. The counting circuit is configured to count a number of occurrences of avalanche current which is caused to occur by avalanche multiplication in the first readout.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

Abstract: An image sensor is disclosed. In some implementations, the image sensor includes a substrate including one or more photoelectric conversion elements arranged in the substrate and structured to convert light into electrical signals representing an image carried by the light, and a plurality of metal layers arranged at different distances from a surface of the substrate and located below the one or more photoelectric conversion elements, each of the metal layers including one or more metal patterns. The one or more metal patterns of the plurality of metal layers are arranged in a concave shape facing the photoelectric conversion element such that incident light reflected by metal layers converges toward the photoelectric conversion element.

Abstract: An image sensor includes a pixel with a photosensitive region accommodated within a semiconductor substrate and a MOS capacitive element with a conducting electrode electrically isolated by a dielectric layer. The dielectric layer forms an interface with both the photosensitive region and the semiconductor substrate, the interface of the dielectric layer including charge traps. A control circuit biases the electrode of the MOS capacitive element with a charge pumping signal designed to generate an alternation of successive inversion regimes and accumulation regimes in the photosensitive region. The charge pumping signal produces recombinations of photogenerated charges in the charge traps of the interface of the dielectric layer and the generation of a substrate current to empty recombined photogenerated charges.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: Provided is a semiconductor light receiving device including: a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and including an upper surface portion; a reflecting film formed to cover the upper surface portion of the semiconductor layer and including a principal reflecting region and an upper surface; and an upper electrode formed to cover at least one portion of the upper surface of the reflecting film, and including a junction portion extending through the reflecting file to be provided in contact with the upper surface portion of the semiconductor layer, the junction portion of the upper electrode surrounding a portion of a circumference of the principal reflecting region of the reflecting film, the principal reflecting region being connected to a region of the reflecting film located outside the junction portion, in which the semiconductor light receiving device detects light entering from another side of the semiconductor substrate.

Abstract: Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided.

Abstract: Bias lines are provided for respective columns of pixels, and of a plurality of bias lines, bias lines provided at an interval of 10 mm are connected to a bias power source through a current detector. The remaining bias lines are connected directly to the bias power source without passing through the current detector. In each pixel, if electric charge is generated by a radiation detection element in accordance with the dose of irradiated radiation, a current flows in the bias line in accordance with the generated electric charge. The current detector detects the current flowing in the bias line, and a control unit detects, as the timing of starting irradiation of a radiation, when the detected current (current value) is equal to or greater than a threshold value, and starts radiographing of a radiological image.

Abstract: An article including a nanostructured functional coating disposed on a substrate is described. The functional coating is characterized by both anti-reflection properties and down-converting properties. Related optoelectronic devices are also described.

Abstract: A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.

Abstract: A solid-state imaging device includes: a substrate which is formed of a semiconductor and includes a first surface and a second surface which face opposite sides; a gate insulation film which is formed on a trench formed in the substrate to penetrate the first surface and the second surface; and a gate electrode which is embedded in the trench through the gate insulation film to be exposed to a second surface side of the substrate. A step difference is formed from the second surface of the substrate to a tip end surface of the gate electrode on the second surface side.

Abstract: A solid-state image pickup device includes: a photoelectric conversion portion formed on a substrate and composed of a photodiode; an image pickup area in which plural pixels each including a reading-out electrode for reading out signal electric charges generated and accumulated in the photoelectric conversion portion are formed; and a light blocking film having an opening portion right above the photoelectric conversion portion in an effective pixel area of the image pickup area, and light-blocking said photoelectric conversion portion in an OB pixel area of the image pickup area, in which a film deposited between the light blocking film and the substrate right above the photoelectric conversion portion in the OB pixel area is composed of only a silicon oxide film.

Abstract: A semiconductor light detection device fabrication technique is provided in which the cap etch and anti-reflection coating steps are performed in a single, self-aligned lithography module.

Abstract: Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: This substrate (11) for a device (50) that collects or emits radiation comprises a transparent polymer layer (1) and a barrier layer (2) on at least one face (1A) of the polymer layer. The barrier layer (2) consists of an antireflection multilayer of at least two thin transparent layers (21, 22, 23, 24) having both alternately lower and higher refractive indices and alternately lower and higher densities, wherein each thin layer (21, 22, 23, 24) of the constituent multilayer of the barrier layer (2) is an oxide, nitride or oxynitride layer.

Abstract: Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes.

Abstract: This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Abstract: A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer.

Abstract: A method for fabricating an image sensor having a pixel region and a logic region, which includes one of: (1) forming a photodiode in a substrate at the pixel region, (2) forming a first interlayer insulating layer on the substrate, (3) forming a first stop film on the first interlayer insulating layer, (4) forming an insulating film on the first stop film, (5) forming a second stop film on the insulating film, (6) forming at least one trench by selective etching of the second stop film and the insulating film positioned at the pixel region for exposing the first stop film, (7) forming conductive material on the second stop film to fill the at least one trench, and (8) forming a zero wiring layer in the at least one trench by planarizing the conductive material until the second stop film is exposed.

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.

Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract: A solar energy utilization device wherein the surface of the incident light side of the transparent base material 1 is covered by water-and-oil-shedding transparent fine particles 5 being bound and fixed to the surface. A method for manufacturing a solar energy utilization device comprising process A of manufacturing reactive transparent fine particles 9 with the first functional group at one end; process B of manufacturing reactive transparent base material 4 with the second functional group at one end forming a covalent bond with the first functional group; process C of manufacturing transparent base material 10 by reacting the reactive transparent fine particles 9 with the reactive transparent base material 4 for binding and fixing the reactive transparent fine particles 9 to the surface; and process D of forming water-and-oil-shedding coating 16 on the surface of the transparent fine particles 5 being bound and fixed to the surface of the transparent base material 10.

Abstract: A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.

Abstract: A method of fabricating a solar cell includes forming an emitter layer of a second conductive type on a front surface and a back surface of a substrate of a first conductive type opposite to the second conductive type, forming an anti-reflection layer on the front surface of the substrate, partially removing the anti-reflection layer and the emitter layer to form an isolation groove dividing the emitter layer into a plurality of regions, removing a portion of the emitter layer formed on the back surface of the substrate, and forming a passivation layer covering the isolation groove and the back surface of the substrate.

Abstract: The present invention provides a substrate connection type module structure comprising a substrate with a through hole structure and a first contact pad. A chip is configured on the through hole structure of the substrate, with a second contact pad and a sensing area. The first contact pad is coupled to the second contact pad via a wire. A second substrate is electrically connected to the first substrate. The second substrate and the chip are located at the same layer. A lens holder is disposed on the substrate, and a lens is located on the top of the lens holder. A transparent material is disposed within the lens holder. The lens is substantially aligning to the transparent material and the sensing area.

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Abstract: Provided is a single junction type CIGS thin film solar cell, which includes a CIGS light absorption layer manufactured using a single junction. The single junction type CIGS thin film solar cell includes a substrate, a back contact deposited on the substrate, a light absorption layer deposited on the back contact and including a P type CIGS layer and an N type CIGS layer coupled to the P type CIGS layer using a single junction, and a reflection prevention film deposited on the light absorption layer.

Abstract: A photovoltaic device including a semiconductor substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first passivation layer on the first surface; and a second passivation layer on the second surface, wherein each of the first passivation layer and the second passivation layer comprises an aluminum-based compound, is disclosed. A method of preparing a photovoltaic device, the method including: forming a semiconductor substrate to have a first surface and a second surface, the second surface being opposite to the first surface; forming an emitter region and a back surface field (BSF) region at the second surface; and forming a first passivation layer on the first surface and a second passivation layer on the second surface, wherein the first passivation layer and the second passivation layer are formed concurrently, is also disclosed.

Abstract: A semiconductor light receiving element comprises: a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a non-doped semiconductor light absorbing layer formed on the semiconductor layer of the first conductivity type, a semiconductor layer of a second conductivity type formed on the non-doped semiconductor light absorbing layer, and an electro-conductive layer formed on the semiconductor layer of the second conductivity type. A plurality of openings, periodically arrayed, are formed in a laminated body composed of the electro-conductive layer, the semiconductor layer of the second conductivity type, and the non-doped semiconductor light absorbing layer. The widths of the openings are less than or equal to the wavelength of incident light, and the openings pass through the electro-conductive layer and the semiconductor layer of the second conductivity type to reach the non-doped semiconductor light absorbing layer.

Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.

Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.

Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.