Abstract: A thin film transistor with favorable electric characteristics is provided, which includes a gate electrode layer; a first insulating layer covering the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions, which are provided with a distance therebetween and at least partly overlap with the gate electrode layer; a microcrystalline semiconductor layer which is provided over the first insulating layer in part of a channel formation region, and at least partly overlaps with the gate electrode layer and does not overlap with at least one of the pair of impurity semiconductor layers; a second insulating layer between and in contact with the first insulating layer and the microcrystalline semiconductor layer; and an amorphous semiconductor layer over the first insulating layer, covering the second insulating layer and the microcrystalline semiconductor layer. The first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.

Abstract: Disclosed is a thin film transistor which is characterized by including a gate electrode 3, a gate insulating film 4, a channel layer 5 and source/drain layers 7, 8 stacked over a substrate 2 in this order or in reverse order, wherein the source/drain layers 7, 8 include n-type microcrystalline silicon layers 7a, 8a and n-type amorphous silicon layers 7b, 8b, which are so arranged that the n-type microcrystalline silicon layers 7a, 8a are on the channel layer 5 side. Also disclosed are a method for manufacturing such a thin film transistor and a display.

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: In a bottom-gate-type thin film transistor used in a liquid crystal display device in which a poly-Si layer and an a-Si layer are stacked, a quantity of an ON current which flows in the thin film transistor can be increased. A poly-Si layer and an a-Si layer are stacked on a gate electrode as an active layer by way of a gate insulation film therebetween in order of the poly-Si layer and the a-Si layer. An n+Si layer and a source/drain layer are formed on the a-Si layer thus forming a thin film transistor. A forward current which flows in the thin film transistor mainly flows in the poly-Si layer.

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract: A display device including the thin film transistor, and a method of manufacturing the display device are provided. The thin film transistor comprising a first gate electrode, a second gate electrode formed on the first gate electrode, a first semiconductor formed on the first gate electrode and including a polycrystalline semiconductor, a second semiconductor formed on the second gate electrode and including an amorphous semiconductor.

Abstract: Provided is a method of manufacturing a nitride-based semiconductor LED including sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate; forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer; heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed; removing the Pd/Zn alloy layer formed on the p-type nitride semiconductor layer; mesa-etching portions of the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.

Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer and crystallized using a metal catalyst, and source and drain electrodes disposed on the semiconductor layer and electrically connected to source and drain regions of the semiconductor layer. A second metal is diffused into a surface region of the semiconductor layer, to getter the metal catalyst from a channel region of the semiconductor layer. The second metal can have a lower diffusion coefficient in silicon than the metal catalyst.

Abstract: The present invention relates to a liquid crystal display and a fabricating method thereof. The cell gaps for the red, green and blue pixel areas are formed in a separate manner for correcting the color shift to enhance image quality. Openings for controlling the cell gaps are provided in the protective layer and the gate insulating layer and have a zigzag-shaped boundary. In this way, the light leakage near the boundary of the openings can be prevented.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: A liquid crystal display panel includes: a thin film transistor array substrate having a gate line and a data line provided on the substrate; a gate insulating film between the gate line and the data line; a thin film transistor having a source electrode, a drain electrode and a gate electrode; a pixel electrode; a protective film for protecting the thin film transistor; a plurality of pads; a transparent electrode pattern formed on the data line, source electrode and drain electrode; and a color filter array substrate joined to the thin film transistor array substrate so that the color filter substrate does not overlap the pad area of the thin film transistor array substrate, wherein at least one of the gate insulating film and protective film in the pad area is etched using the color filter array substrate as a mask to expose at least one of the plurality of pads.

Abstract: An electro-luminescence device including an electro-luminescence element and a thin film transistor electrically connected to the electro-luminescence element. The thin film transistor includes a gate electrode formed over a substrate, an insulating layer formed over the gate electrode, and a first semiconductor pattern formed over the insulating layer. An etch stop layer is formed over the first semiconductor layer. A second semiconductor pattern is formed over the etch stop layer at one side of the etch stop layer, and a third semiconductor pattern is formed over the etch stop layer at another side of the etch stop layer. A source electrode is formed over the second semiconductor pattern, and a drain electrode is formed over the third semiconductor pattern.

Abstract: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.

Abstract: To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.

Abstract: A thin-film transistor substrate in which an aluminum alloy film composing a source/drain wiring is directly connected with a transparent electrode. The thin-film transistor substrate includes a gate wiring, and source wiring and drain wiring, the gate wiring and the source and drain wiring being arranged orthogonally to each other. The single-layer aluminum alloy film composing the gate wiring and the single-layer aluminum alloy film composing the source wiring and the drain wiring are the same in composition. Furthermore, display devices can be mounted with the above thin-film transistor substrates.

Abstract: A light emitting device is disclosed. The light emitting device includes a substrate including a thin film transistor, an insulating film disposed over the thin film transistor, a first electrode disposed over the thin film transistor and connected to the thin film transistor, a function layer including at least one of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are sequentially disposed over the first electrode, and a second electrode disposed on the function layer. A thickness of the first electrode is substantially 0.29 to 0.35 times a thickness of the function layer. A thickness of the second electrode is substantially 0.29 to 0.69 times the thickness of the function layer.

Abstract: A method of fabricating an LCD device includes forming a gate line, a gate electrode, a gate pad electrode at an end of the gate line, and a common line on a substrate; forming a gate insulating layer on the gate electrode; forming an active layer on the gate insulating layer; forming an etch stopper on the active layer; forming first and second ohmic contact layers spaced apart from each other on the active layer and an impurity-doped amorphous silicon pattern contacting the gate insulating layer therebelow, outer sides of the first and second ohmic contact layers being outside the active layer; forming a data line crossing the gate line to define a pixel region, a data pad electrode at an end of the data line, and source and drain electrodes on the first and second ohmic contact layers, respectively; forming a pixel electrode and a common electrode in the pixel region to induce an in-plane electric field; and forming a gate pad terminal electrode on the gate pad electrode.

Abstract: A boron phosphide-based compound semiconductor device with excellent device properties, comprising a boron phosphide-based compound semiconductor layer having a wide bandgap is provided. The boron phosphide-based compound semiconductor layer consists of an amorphous layer and a polycrystal layer provided to join with the amorphous layer, and the room-temperature bandgap of the boron phosphide-based compound semiconductor layer is from 3.0 eV to less than 4.2 eV.

Abstract: A thin film transistor manufacturing method includes the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film only in the region which will serve as a channel region of the amorphous silicon film; and forming an n-plus silicon film and metal layer on top of the channel protective film and amorphous silicon film in succession. The method further includes the step of patterning the amorphous silicon film and n-plus silicon film to selectively leave the region associated with source and drain electrodes, using the channel protective film as an etching stopper to selectively remove the region of the n-plus silicon film and metal layer associated with the channel region so as to form source and drain regions from the n-plus silicon film and also form source and drain electrodes from the metal layer.

Abstract: A light-emitting diode includes a substrate, a compound semiconductor layer including a p-n junction-type light-emitting part formed on the substrate, an electric conductor disposed on the compound semiconductor layer and formed of an electrically conductive material optically transparent to the light emitted from the light-emitting part and a high resistance layer possessing higher resistance than the electric conductor and provided in the middle between the compound semiconductor layer and the electric conductor. In the configuration of a light-emitting diode lamp, the electric conductor and the electrode disposed on the semiconductor layer on the side opposite to the electric conductor across the light-emitting layer are made to assume an equal electric potential by means of wire bonding. The light-emitting diode abounds in luminance and excels in electrostatic breakdown voltage.

Abstract: The present invention relates to a various systems for generating and directing electron flow, and related methods, manufacturing techniques and related componentry, such as can be used in lithography, microscopy and other applications. In one embodiment, the present invention involves a system that includes an electron source having a plurality of independently-actuatable emission surfaces each of which is capable of emitting electrons, and an optical column adjacent to the electron source through which the emitted electrons pass. The optical column includes a plurality of actuatable electrodes that are capable of influencing paths taken by the emitted electrons.

Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Abstract: A boron phosphide-based semiconductor light-emitting device, comprising: a crystalline substrate; a first semiconductor layer formed on said crystalline substrate, said first semiconductor layer including a light-emitting layer, serving as a base layer and having a first region and a second region different from the first region; a boron phosphide-based semiconductor amorphous layer formed on said first region of said first semiconductor layer, said boron phosphide-based semiconductor amorphous layer including a high-resistance boron phosphide-based semiconductor amorphous layer or a first boron phosphide-based semiconductor amorphous layer having a conduction type opposite to that of said first semiconductor layer; a pad electrode formed on said high-resistance or opposite conductivity-type boron phosphide-based semiconductor amorphous layer for establishing wire bonding; and a conductive boron phosphide-based crystalline layer formed on said second region of said first semiconductor layer, said conductive b

Abstract: The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3 in average and comprises a plurality of needle-shaped silicon crystallites. In another aspect, the present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3, comprises a plurality of needle-shaped silicon crystallites and is formed on an insulating substrate. Such a polysilicon film according to the present invention avoids metal contamination usually generated in a conventional method of metal induced crystallization.

Abstract: The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3 on average and comprises a plurality of needle-shaped silicon crystallites. In another aspect, the present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3, comprises a plurality of needle-shaped silicon crystallites and is formed on an insulating substrate. Such a polysilicon film according to the present invention avoids metal contamination usually generated in a conventional method of metal induced crystallization.

Abstract: A thin film transistor (TFT) having a lightly doped drain (LDD) structure includes a lightly doped drain (LDD) region formation pattern, an active layer formed in an uneven structure on the LDD region formation pattern, and having a source region and a drain region having an LDD region. A gate electrode may be formed on a gate insulating layer, and source and drain electrodes are coupled to the source and drain regions.

Abstract: An array substrate for a liquid crystal display device comprises a gate line on a substrate having a pixel region; a gate insulating layer on the gate line; a data line crossing the gate line to define the pixel region and formed on the gate insulating layer; a thin film transistor in the pixel region and connected to the gate line and the data line; a passivation layer on the thin film transistor and the data line and having a groove extending along boundary portion of the pixel region and exposing the gate insulating layer; and a pixel electrode in the pixel region and connected to the thin film transistor.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

Abstract: A method for manufacturing polysilicon layer is provided. At first, a substrate is provided. An amorphous silicon layer having a second region and a first region is formed on the substrate. The first region is thicker than the second region. The amorphous silicon layer is completely melted to form a melted amorphous silicon layer having a first melted region and a second melted region. The temperature of the bottom center of the first melted region is lower than that of the second melted region and that of the top of the first melted region. The melted amorphous silicon layer is crystallized to form a polysilicon layer. The crystallization begins from the bottom center of the first melted region to the second melted region and the top of the first melted region.