Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode in this order, wherein the memory layer includes a high resistance layer which includes tellurium (Te) as the chief component among anion components and is formed on the first electrode side; and an ion source layer which includes at least one kind of metal element and at least one kind of chalcogen element among tellurium (Te), sulfur (S) and selenium (Se) and is formed on the second electrode side.

Abstract: Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.

Abstract: Phase transitions (such as metal-insulator transitions) are induced in oxide structures (such as vanadium oxide thin films) by applying an electric field. The electric field-induced phase transitions are achieved in VO2 structures that scale down to nanometer range. In some embodiments, the optical and/or dielectric properties of the oxide structures are actively tuned by controllably varying the applied electric field. Applying a voltage to a single-phase oxide material spontaneously leads to the formation of insulating and conducting regions within the active oxide material. The dimensions and distributions of such regions can be dynamically tuned by varying the applied electric field and/or the temperature. In this way, oxide materials with dynamically tunable optical and/or dielectric properties are created.

Abstract: A memristive device (400) includes: a first electrode (405); a second electrode (425); a memristive matrix (415) interposed between the first electrode (405) and the second electrode (425); a porous dopant diffusion element (410) in physical contact with the memristive matrix (415) and in proximity to the first electrode (405) and the second electrode (425); and a first mobile dopant species which moves through the porous dopant diffusion element (410) in response to a programming electrical field.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A method for formation of a phase change memory (PCM) cell includes depositing amorphous phase change material in a via hole, the via hole comprising a bottom and a top, such that the amorphous phase change material is grown on an electrode located at the bottom of the via hole; melt-annealing the amorphous phase change material; and crystallizing the phase change material starting at the electrode at the bottom of the via hole and ending at the top of the via hole.

Abstract: It is an object of the present invention to provide a high-performance and high reliable semiconductor device and to provide a technique of manufacturing the semiconductor device at low cost with high yield. The semiconductor device is manufactured by steps of forming a first conductive layer, forming a first liquid-repellent layer over the first conductive layer, discharging a composition containing a material for a mask layer over the first liquid-repellent layer to form a mask layer, processing the first liquid-repellent layer with the use of the mask layer, forming a second liquid-repellent layer, forming an insulating layer over the first conductive layer and the second conductive layer, and forming a second conductive layer over the insulating layer.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0<x?0.

Abstract: A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.

Abstract: A memory cell includes a first electrode, a second electrode, and a first portion of phase-change material contacting the first electrode. The memory cell includes a second portion of phase-change material contacting the second electrode and a third portion of phase-change material between the first portion and the second portion. A phase-change material composition of the third portion and the second portion gradually transitions from the third portion to the second portion.

Abstract: A eutectic memory includes a eutectic memory material layer, a top and a bottom electrodes, or a left and a right electrodes. Materials of the eutectic memory layer are represented by M1-M2-X wherein the M1 is a semiconductor element, the M2 is a metallic element which forms eutectic with the M1, and the X is an unavoidable impurity or an added element.

Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract: A semiconductor memory device includes a first electrode and a second electrode, a variable resistance material pattern including a first element disposed between the first and second electrode, and a first spacer including the first element, the first spacer disposed adjacent to the variable resistance material pattern.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Abstract: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.

Abstract: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom.

Abstract: A phase change memory includes a volume of phase change material disposed between, and coupled to, two electrodes, with the composition of a region of at least one of the two electrodes or phase change material having been compositionally altered to reduce the programmed volume of the phase change material.

Abstract: A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.

Abstract: A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

Abstract: A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom electrode contact in contact with the switching device through a first contact area and in contact with the phase-change layer through a second contact area, which is smaller than the first contact area.

Abstract: A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode.

Abstract: A voltage memory switch may be formed of an amorphous semiconductor threshold switch and a select device. The amorphous threshold switch may be latched into one of two different current conducting levels. Then, in some embodiments, a relatively dense memory array can be achieved by maintaining an appropriate bias on the cell to prevent it from losing the programmed state.

Abstract: Nitrogen-doped MgO insulating layers exhibit voltage controlled resistance states, e.g., a high resistance and a low resistance state. Patterned nano-devices on the 100 nm scale show highly reproducible switching characteristics. The voltage levels at which such devices are switched between the two resistance levels can be systematically lowered by increasing the nitrogen concentration. Similarly, the resistance of the high resistance state can be varied by varying the nitrogen concentration, and decreases by orders of magnitude by varying the nitrogen concentrations by a few percent. On the other hand, the resistance of the low resistance state is nearly insensitive to the nitrogen doping level. The resistance of single Mg50O50-xNx layer devices can be varied over a wide range by limiting the current that can be passed during the SET process. Associated data storage devices can be constructed.

Abstract: A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.

Abstract: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.

Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion.

Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element.

Abstract: A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.

Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.

Abstract: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.

Abstract: Provided are a phase-change nonvolatile memory device and a manufacturing method thereof. The device includes: a substrate; and a stack structure disposed on the substrate and including a phase-change material layer. The phase-change material layer is formed of an alloy of antimony (Sb) and zinc (Zn), so that the phase-change memory device can stably operate at high speed and reduce power consumption.

Abstract: A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract: A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.

Abstract: A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.

Abstract: A multi-bit phase-change memory device includes a semiconductor substrate with a plurality of phase-change patterns sequentially stacked above the semiconductor substrate. Each phase-change pattern crosses another phase change pattern, and each phase change pattern includes a phase-change conductive line formed on a surface thereof. Bipolar transistors are installed between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns, and the bipolar transistors selectively form electrical connections between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns. Heating electrodes are aligned between the respective bipolar transistors and phase-change patterns. The semiconductor substrate includes an active area that extends in a direction that is perpendicular to the extension direction of the lowermost phase-change pattern.

Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A method for fabricating a phase change memory (PCM) cell includes forming a dielectric layer over an electrode, the electrode comprising an electrode material; forming a via hole in the dielectric layer such that the via hole extends down to the electrode; and growing a single crystal of a phase change material on the electrode in the via hole. A phase change memory (PCM) cell includes an electrode comprising an electrode material; a dielectric layer over the electrode; a via hole in the dielectric layer; and a single crystal of a phase change material located in the via hole, the single crystal contacting the electrode at the bottom of the via hole.

Abstract: The present invention relates to asymmetric molecular bilayers for the use in the junctions of electronic devices, such as crossbar junctions, comprising the general structure ET-MT( )MB-EB, wherein ET and EB denote a top and a bottom electrode, MT and MB represent functional molecules both forming a self-assembled monolayer (SAM) on said top or bottom electrode, and the symbol ( ) denotes a non-covalent interaction between the two monolayers, resulting in a molecular bilayer, sandwiched between the two electrodes. The electrodes are solid state electrodes and stationary with respect to each other. The present invention also relates to a method of producing such assemblies.

Abstract: Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.

Abstract: An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element.