Abstract: A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

Abstract: A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant conce

Abstract: A method of forming can be provided by forming a metal silicide layer that includes a diffusion metal on a substrate. A native oxide layer can be formed on the metal silicide layer and forming a metal oxide layer by reacting the native oxide layer with the diffusion metal. A phase-change layer and an upper electrode can be formed on the metal oxide layer. A phase-change memory device can include a substrate and a conductive region on the substrate with a lower electrode on the conductive region, where the lower electrode can include a metal silicide layer on the conductive region and a metal silicon nitride layer having a resistivity of about 10 to about 100 times that of the metal silicide layer. A metal oxide layer can be located between the metal silicon nitride layer and the metal silicide layer, the metal oxide layer comprising a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.

Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.

Abstract: A phase-change memory cell structure includes a bottom diode on a substrate; a heating stem on the bottom diode; a first dielectric layer surrounding the heating stem, wherein the first dielectric layer forms a recess around the heating stem; a phase-change storage cap capping the heating stem and the first dielectric layer; and a second dielectric layer covering the first dielectric layer and the phase-change storage cap wherein the second dielectric layer defines an air gap in the recess.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.

Abstract: A device is disclosed having a M8XY6 layer sandwiched in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Also disclosed is a device comprising: an MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and wherein a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area. Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode.

Abstract: An embodiment of the invention provides a magnetoresistance element with an MR ratio higher than that of the related art and a method of manufacturing the same. A magnetoresistance element includes a substrate, a first crystalline ferromagnetic layer, a tunnel barrier layer, a second crystalline ferromagnetic layer, a nonmagnetic intermediate layer, and a third crystalline ferromagnetic layer. The first ferromagnetic layer is made of an alloy containing Co atoms, Fe atoms, and B atoms. The tunnel barrier layer includes a crystalline magnesium oxide layer or a crystalline boron magnesium oxide layer. The second ferromagnetic layer is made of an alloy containing Co atoms and B atoms or an alloy containing Co atoms and Fe atoms. The third ferromagnetic layer is made of an alloy containing Ni atoms and Fe atoms.

Abstract: A memristive device (200) includes a first electrode (104); a second electrode (102); a junction (106) between the first electrode (104) and the second electrode (102), the junction (106) including a semiconductor matrix (230) and particles (240) embedded in the semiconductor matrix (230), the particles (240) being configured to hold a selectable level of electrical charge, the electrical charge controlling the amount of current flowing through the junction (106) for a given reading voltage.

Abstract: A configurable memristive device (300) for regulating an electrical signal includes a memristive matrix (350) containing a first dopant species; emitter (320), collector (310), and a base electrodes (330, 340) which are in contact with the memristive matrix (350); and a mobile dopant species contained within a central region (360) contiguous with the base electrodes (330, 340), the mobile dopant species moving within the memristive matrix (350) in response to a programming electrical field. A method of configuring and using a memristive device (300) includes: applying a programming electrical field across a memristive matrix (350) such that a mobile dopant species creates a central doped region (360) which bisects the memristive matrix (350); and applying a control voltage to the central doped region (360) to regulate current flow between an emitter electrode (320) and a collector electrode (310).

Abstract: A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.

Abstract: A memristor having an active region having a first electrode, a second electrode, and a nanostructure connecting the first electrode with the second electrode. The nanostructure includes a generally insulating material configured to have an electrically conductive channel formed in the material. The nanostructure forms the active region and has a length and a thickness, where the length is substantially equivalent to a distance extending from the first electrode to the second electrode along the nanostructure and the thickness is a distance across the nanostructure substantially perpendicular to the length of the nanostructure. The length of the nanostructure is substantially greater than the thickness of the nanostructure.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.

Abstract: Bipolar memory cells and a memory device including the same are provided, the bipolar memory cells include two bipolar memory layers having opposite programming directions. The two bipolar memory layers may be connected to each other via an intermediate electrode interposed therebetween. The two bipolar memory layers may have the same structure or opposite structures.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device may include a lower electrode having a hollow cylindrical shape of which an upper portion is open, the lower electrode being disposed on a substrate, an insulating structure wrapping the lower electrode and including a nitride, a variable resistance pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the variable resistance pattern.

Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.

Abstract: A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.

Abstract: A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are formed to come into contact with the heaters. The heaters have horizontal cross-sectional bent shapes which can have any number of shapes such as a shape similar to that of a boomerang. The horizontal cross-sectional bent shapes of the heaters are for minimizing the contact area between the heaters and the phase change layer so that programming currents can be reduced or minimized.

Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

Abstract: A method of forming a reversible resistance-switching metal-carbon-metal (“MCM”) device is provided, the device including a first conducting layer, a second conducting layer, and a reversible resistance-switching element disposed between the first and second conducting layers, wherein the reversible resistance-switching element includes thermal CVD graphitic material and includes a highly resistive region that favors crack formation. Other aspects are also provided.

Abstract: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

Abstract: A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated top and bottom electrodes having mutually opposed contact surfaces. A sub-lithographic pillar of memory material, which in a particular embodiment is a chalcogenide, is encased within the dielectric material layer. A heater between the pillar of programmable resistive material and the top electrode forms an active region, or programmable resistive change region, next to the heater when the memory device is programmed or reset.

Abstract: A phase change memory device having an increased sensing margin for improved cell efficiency. The phase change memory device includes a plurality of diodes formed in an active region of a semiconductor substrate; an insulation layer pattern formed on the respective diodes; a phase change layer formed on the insulation layer pattern in such a way as not to be electrically connected with the diodes; bit lines formed over the phase change layer; and a global X-decoder line formed over the bit lines. The present invention suppresses current flow in a phase change memory device because the dummy cell string and the dummy active region are not electrically connected with each other under the global X-decoder line, whereby preventing parasitic current from being produced in the phase change memory device.

Abstract: A method of at least one embodiment of the present invention of manufacturing a solid-state memory is a method of manufacturing a solid-state memory, the solid-state memory including a recording film whose electric characteristics are varied by phase transformation, the method including: forming the recording film by forming a laminate of two or more layers so that a superlattice structure is provided, each of the layers having a parent phase which shows solid-to-solid phase-transformation, the recording film being formed at a temperature not lower than a temperature highest among crystallization temperatures of the parent phases. It is thus possible to manufacture a solid-state memory which requires lower current for recording and erasing data and has a greater rewriting cycle number.

Abstract: A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.

Abstract: An electronic device includes a first electrode, a second electrode and a nanowire connected between the first and second electrodes to allow electric current flow. The nanowire is made from a conductive material exhibiting a variable resistance due to electromigration. The nanowire is repeatably switchable between two states. A voltage clamp operates through feedback control to maintain the voltage across the nanowire and prevent thermal runaway.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.

Abstract: A chalcogenide film of the present invention is deposited, by sputtering, in a contact hole formed in an insulating layer on a substrate. The chalcogenide film comprises an underlayer film formed at least on a bottom portion of the contact hole and a crystal layer made of a chalcogen compound, and formed onto the underlayer film and in the contact hole.

Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).

Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

Abstract: In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided.

Abstract: Provided are resistance memory devices and methods of forming the same. The resistance memory devices include a first electrode and a second electrode on a substrate, a transition metal oxide layer interposed between the first electrode and the second electrode, an electrolyte layer interposed between the second electrode and the transition metal oxide layer, and conductive bridges having one end that is electrically connected to the second electrode on the electrolyte.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material.

Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.

Abstract: Phase changeable memory devices are provided including a mold insulating layer on a substrate, the mold insulating layer defining an opening therein. A phase-change material layer is provided in the opening. The phase-change material includes an upper surface that is below a surface of the mold insulating layer. A first electrode is provided in the opening and on the phase-change material layer. A spacer is provided between a sidewall of the mold insulating layer and the phase-change material layer and the first electrode. The upper surface of the first electrode is coplanar with the surface of the mold insulating layer. Related methods are also provided.

Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical held. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes.

Abstract: A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.

Abstract: Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.

Abstract: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

Abstract: A memristive routing device (200) includes a memristive matrix (240), mobile dopants (255) moving with the memristive matrix (240) in response to programming electrical fields and remaining stable within the memristive matrix (240) in the absence of the programming electrical fields; and at least three electrodes (210, 220, 230) surrounding the memristive matrix (240). A method for tuning electrical circuits with a memristive device (900) includes measuring a circuit characteristic (805) and applying a programming voltage to the memristive device (900) which causes motion of dopants within the memristive device (900) to alter the circuit characteristic (805).

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a spatially varying region of the active region prior to device actuation. The at least two dopants have opposite conductivity types and different mobilities.

Abstract: Phase transition devices may include a functional layer made of functional material that can undergo a change in conductance in response to an external stimulus such as an electric or magnetic or optical field, or heat. The functional material transitions between a conducting state and a non-conducting state, upon application of the external stimulus. A capacitive device may include a functional layer between a top electrode and a bottom electrode, and a dielectric layer between the functional layer and the top electrode. A three terminal phase transition switch may include a functional layer, for example a conductive oxide channel, deposited between a source and a drain, and a gate dielectric layer and a gate electrode deposited on the functional layer. An array of phase transition switches and/or capacitive devices may be formed on a substrate, which may be made of inexpensive flexible material.

Abstract: The present invention discloses a memory system comprising a plurality of crystals, and at least two conductors. The at least two conductors being orthogonal to each other. Wherein at least one of the plurality of crystals are bounded by the orthogonal intersection of the at least two conductors.